ICS854S058AGILF IDT, Integrated Device Technology Inc, ICS854S058AGILF Datasheet
ICS854S058AGILF
Specifications of ICS854S058AGILF
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ICS854S058AGILF Summary of contents
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Differential-to-LVDS Clock Multiplexer General Description The ICS854S058I is an 8:1 Differential-to-LVDS Clock ICS Multiplexer which can operate up to 2.5GHz. The ICS854S058I has 8 selectable differential clock inputs. HiPerClockS™ The PCLK, nPCLK input pairs can accept LVPECL, LVDS or ...
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ICS854S058I Datasheet Table 1. Pin Descriptions Number Name 1 PCLK0 2 nPCLK0 3 PCLK1 4 nPCLK1 SEL0, SEL1, SEL2 9 PCLK2 10 nPCLK2 11 PCLK3 12 nPCLK3 13 nPCLK4 14 PCLK4 15 nPCLK5 ...
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ICS854S058I Datasheet Table 3. Clock Input Function Table Inputs SEL2 SEL1 0 (default Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings ...
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ICS854S058I Datasheet Table 4B. LVCMOS/LVTTL DC Characteristics, V Symbol Parameter V Input High Voltage IH V Input Low Voltage IL I Input High Current SEL[0: Input Low Current SEL[0:2] IL Table 4C. LVPECL Differential DC Characteristics, V Symbol ...
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ICS854S058I Datasheet Table 5. AC Characteristics Symbol Parameter f Output Frequency OUT t Propagation Delay; NOTE 1 PD Buffer Additive Phase Jitter, tjit(Ø) RMS; Refer to Additive Phase Jitter Section tsk(pp) Part-to-Part Skew; NOTE 2, 3 tsk(i) Input ...
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ICS854S058I Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...
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ICS854S058I Datasheet Parameter Measurement Information V DD 3.3V±5% POWER SUPPLY LVDS + Float GND – 3.3V LVDS Output Load AC Test Circuit nPCLK[0:7] PCLK[0: Propagation Delay nQ 80% 20 Output Rise/Fall Time ICS854S058AGI ...
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ICS854S058I Datasheet Parameter Measurement Information, continued V DD LVDS DC Input ➤ Offset Voltage Setup Spectrum of Output Signal Q A0 MUX = A0 – A1 _ISOL A1 ƒ (fundamental) MUX Isolation Application Information Recommendations for Unused Input Pins Inputs: ...
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ICS854S058I Datasheet LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, SSTL and other differential signals. The differential signal must meet the V V input requirements. Figures show interface examples CMR for the PCLK/nPCLK input driven ...
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ICS854S058I Datasheet Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This ...
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ICS854S058I Datasheet Schematic Example An application schematic example of ICS854S058I is shown in Figure 4. The inputs can accept various types of differential signals. In this example, the inputs are driven by LVDS drivers. The transmission lines are assumed to ...
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ICS854S058I Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS854S058I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S058I is the sum of the core ...
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ICS854S058I Datasheet Reliability Information Table 7. θ vs. Air Flow Table for a 24 Lead TSSOP JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS854S058I is: 446 This device is pin and ...
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ICS854S058I Datasheet Ordering Information Table 9. Ordering Information Part/Order Number Marking 854S058AGILF ICS854S058AIL 854S058AGILFT ICS854S058AIL NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented ...
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ICS854S058I Datasheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described ...