ICS854S058AGILF IDT, Integrated Device Technology Inc, ICS854S058AGILF Datasheet - Page 10

• Manufacturer Part Number: ICS854S058AGILF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS854S058AGILF

• Lead Free Status / RoHS Status: Compliant

ICS854S058I Datasheet
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
0.609.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 3. In a 100Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100Ω across near the receiver input. For a multiple
Figure 3. Typical LVDS Driver Termination
ICS854S058AGI REVISION A DECEMBER 11, 2009
3.3V
LVDS Driver
100 Differential Transmission Line
DD
= 3.3V, V_REF should be 1.25V and R2/R1 =
50
50
DD
R1
100
/2 is
10
Figure 2. Single-Ended Signal Driving Differential Input
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
+
–
3.3V
CLK_IN
0.1uF
C1
R1
1K
V_REF
R2
1K
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
V
DD
PCLKx
nPCLKx
©2009 Integrated Device Technology, Inc.