ICS854S058AGILF IDT, Integrated Device Technology Inc, ICS854S058AGILF Datasheet - Page 2

• Manufacturer Part Number: ICS854S058AGILF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS854S058AGILF

• Lead Free Status / RoHS Status: Compliant

ICS854S058I Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
ICS854S058AGI REVISION A DECEMBER 11, 2009
Symbol
C
R
R
Number
VDD
IN
PULLDOWN
6, 7, 8
18, 19
5, 20
10
11
12
13
14
15
16
17
21
22
23
24
1
2
3
4
9
/2
SEL0, SEL1, SEL2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
Name
nQ, Q
GND
V
DD
Output
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pullup/
Pullup/
Pullup/
Pullup/
Pullup/
Pullup/
Pullup/
Test Conditions
Non-inverting differential LVPECL clock input.
Non-inverting differential LVPECL clock input.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Power supply ground.
Differential output pair. LVDS interface levels.
Description
Inverting differential LVPECL clock input. V
Inverting differential LVPECL clock input. V
Positive supply pins.
Inverting differential LVPECL clock input. V
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
Inverting differential LVPECL clock input. V
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
Non-inverting differential LVPECL clock input.
2
Minimum
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Typical
DD
DD
DD
DD
DD
DD
DD
DD
75
50
2
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
©2009 Integrated Device Technology, Inc.
Maximum
Units
k
k
pF
Ω
Ω