COM20020I-DZD-TR Standard Microsystems (SMSC), COM20020I-DZD-TR Datasheet - Page 54

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COM20020I-DZD-TR

Manufacturer Part Number
COM20020I-DZD-TR
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of COM20020I-DZD-TR

Number Of Transceivers
1
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
COM20020I-DZD-TR
Manufacturer:
Microchip
Quantity:
1 048
Part Number:
COM20020I-DZD-TR
Manufacturer:
Microchip Technology
Quantity:
10 000
Revision 12-05-06
AD0-AD2,
D3-D7
nWR
nCS
ALE
nRD
*
Note 1:
Note 2:
Note 3:
T
T
T
T
t10
t11
t12
t13
ARB
ARB
ARB
opr
t8
t9
Figure 8.2 – Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
t1
t2
t3
t4
t5
t6
t7
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Cycle Time (nRD Low to Next Time Low)
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5T
leading edge of the next nRD.
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5T
leading edge of nRD.
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
nRD High to Data High Impedance
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
nWR
Address Setup to ALE Low
Address Hold from ALE Low
opr
t9
to nRD Low
t1
if SLOW ARB = 1
VALID
opr
t3
if SLOW ARB = 0
t13
MUST BE: RBUSTMG bit = 0
DATASHEET
t4
t2,
Parameter
Note 3
t5
Page 54
t6
ARB
ARB
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
from the trailing edge of nRD to the
from the trailing edge of nWR to the
t10
t11
VALID DATA
4T
min
20
10
10
10
15
20
20
60
20
20
ARB
0
t8
*
max
40
20
t7
Note 2
units
t12
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SMSC COM20020I Rev D
Datasheet

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