COM20020I-DZD-TR Standard Microsystems (SMSC), COM20020I-DZD-TR Datasheet - Page 60

• Manufacturer Part Number: COM20020I-DZD-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I-DZD-TR

• Number Of Transceivers: 1
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

Revision 12-05-06
D0-D7
A0-A2
DIR
nDS
nCS
**
Note 1:
Note 2:
*
T
T
T
T
t10
t11
ARB
ARB
ARB
opr
t1
t2
t3
t4
t5
t6
t7
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
t8
t9
t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2.
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
Cycle Time (nDS Low to Next Time Low)
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5T
the leading edge of the next nDS.
DIR Setup to nDS Active
DIR Hold from nDS Inactive
nDS Low to Valid Data
nDS High to Data High Impedence
nDS Low Width
nDS High Width
opr
if SLOW ARB = 1
opr
t1
if SLOW ARB = 0
t5
CASE 2: RBUSTMG bit = 1
t3
Parameter
DATASHEET
t8
Page 60
VALID
ARB
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
from the trailing edge of nDS to
t10
t6
VALID DATA
4T
min
ARB
100
10
10
30
-5
-5
0
0
0
*+30
max
60**
20
t9
t7
t2
t4
Note 2
t11
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SMSC COM20020I Rev D
Datasheet