LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 8

• Manufacturer Part Number: LAN9312-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NU

• Number Of Primary Switch Ports: 2
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

14.2.5 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.2.6 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
14.2.7 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
14.2.8 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
14.2.9 Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
14.3
14.3.1 Host MAC Control Register (HMAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
14.3.2 Host MAC Address High Register (HMAC_ADDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
14.3.3 Host MAC Address Low Register (HMAC_ADDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH) . . . . . . . . . . . . . . . . . . . . . . . 275
14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL). . . . . . . . . . . . . . . . . . . . . . . . 276
14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
14.3.7 Host MAC MII Data Register (HMAC_MII_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
14.3.8 Host MAC Flow Control Register (HMAC_FLOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR) . . . . . . . . . . . . . . . . . . . . . 284
14.4
14.4.1 Virtual PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Revision 1.7 (06-29-10)
14.2.4.1
14.2.4.2
14.2.5.1
14.2.5.2
14.2.5.3
14.2.5.4
14.2.5.5
14.2.5.6
14.2.5.7
14.2.5.8
14.2.5.9
14.2.5.10
14.2.5.11
14.2.5.12
14.2.5.13
14.2.5.14
14.2.5.15
14.2.5.16
14.2.5.17
14.2.5.18
14.2.5.19
14.2.5.20
14.2.5.21
14.2.5.22
14.2.5.23
14.2.5.24
14.2.6.1
14.2.6.2
14.2.6.3
14.2.6.4
14.2.6.5
14.2.6.6
14.2.6.7
14.2.6.8
14.2.7.1
14.2.7.2
14.2.8.1
14.2.8.2
14.2.8.3
14.2.8.4
14.2.8.5
14.2.8.6
14.2.8.7
14.2.8.8
14.2.9.1
14.2.9.2
14.2.9.3
14.2.9.4
14.2.9.5
14.2.9.6
14.2.9.7
14.2.9.8
Host MAC Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
EEPROM Command Register (E2P_CMD) .................................................................................................................................................. 197
EEPROM Data Register (E2P_DATA).......................................................................................................................................................... 200
Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x) .......................................................... 201
Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x) .......................................................... 202
Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)..... 203
Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)........................................ 204
Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x).......................................................... 205
Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x) ......................................................... 206
Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) .... 207
Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x) ....................................... 208
GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8).................................................................. 209
GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) ................................................................. 210
GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9).................................................................. 211
GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) ................................................................. 212
1588 Clock High-DWORD Register (1588_CLOCK_HI)............................................................................................................................... 213
1588 Clock Low-DWORD Register (1588_CLOCK_LO) .............................................................................................................................. 214
1588 Clock Addend Register (1588_CLOCK_ADDEND) ............................................................................................................................. 215
1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)................................................................................................... 216
1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) .................................................................................................. 217
1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) ..................................................................... 218
1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO).............................................................. 219
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) ................................................................................................ 220
1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) ............................................................................................. 221
1588 Configuration Register (1588_CONFIG).............................................................................................................................................. 222
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)................................................................................................................ 226
1588 Command Register (1588_CMD) ........................................................................................................................................................ 228
Port 1 Manual Flow Control Register (MANUAL_FC_1)............................................................................................................................... 229
Port 2 Manual Flow Control Register (MANUAL_FC_2)............................................................................................................................... 231
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) ......................................................................................................... 233
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) ........................................................................................................... 235
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) ................................................................................................... 236
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) ........................................................................................................ 238
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) ......................................................................................................... 239
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) ................................................................................. 240
PHY Management Interface Data Register (PMI_DATA) ............................................................................................................................. 243
PHY Management Interface Access Register (PMI_ACCESS) .................................................................................................................... 244
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ......................................................................................................................... 246
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)...................................................................................................................... 248
Virtual PHY Identification MSB Register (VPHY_ID_MSB) .......................................................................................................................... 250
Virtual PHY Identification LSB Register (VPHY_ID_LSB) ............................................................................................................................ 251
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV).................................................................................................... 252
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) .................................................. 254
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) .......................................................................................................... 256
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) .............................................................................. 257
Chip ID and Revision (ID_REV).................................................................................................................................................................... 259
Byte Order Test Register (BYTE_TEST) ...................................................................................................................................................... 260
Hardware Configuration Register (HW_CFG)............................................................................................................................................... 261
Power Management Control Register (PMT_CTRL) .................................................................................................................................... 263
General Purpose Timer Configuration Register (GPT_CFG) ....................................................................................................................... 265
General Purpose Timer Count Register (GPT_CNT) ................................................................................................................................... 266
Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. 267
Reset Control Register (RESET_CTL) ......................................................................................................................................................... 268
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
8
SMSC LAN9312
Datasheet