82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 17

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

2.5
TDn and encoded by AMI or B8ZS/HDB3 line code rules when single rail
mode is configured or pre-encoded data in NRZ format are input on
TDPn and TDNn when dual rail mode is configured. The data are
sampled into the device on falling edges of TCLKn. Jitter attenuator, if
enabled, is provided with a FIFO through which the data to be trans-
mitted are passing. A low jitter clock is generated by an integral digital
phase-locked loop and is used to read data from the FIFO. The shape of
the pulses are user programmable to ensure that the T1/E1 pulse
template is met after the signal passes through different cable lengths or
types. Bipolar violation, for diagnosis, can be inserted on pin BPVIn if
AMI line code rule is enabled.
2.5.1
T1.102, is illustrated in Figure-10. The device has built-in transmit wave-
form templates, corresponding to 5 levels of pre-equalization for cable of
a length from 0 to 655 ft with each increment of 133 ft.
The device has built-in transmit waveform templates for cable of 75
120
ware mode and host mode. In hardware mode, setting pins TS[2:0] can
select the required waveform template for all the transmitters, as shown
in Table-9. In host mode, the waveform template can be configured on a
per-channel basis. Bits TSIA[2:0] in register TSIA are used to select the
channel and bits TS[2:0] in register TS are used to select the required
waveform template.
which is 16XMCLK as the clock reference. This function will be
bypassed when MCLK is unavailable.
IDT82V2044
Functional Description
In transmit path, data in NRZ format are clocked into the device on
T1 pulse template, specified in the DSX-1 Cross-Connect by ANSI
E1 pulse template, specified in ITU-T G.703, is shown in Figure-11.
Any one of the six built-in waveforms can be chosen in both hard-
The built-in waveform shaper uses an internal high frequency clock
Ω
.
TRANSMITTER
WAVEFORM SHAPER
RRINGn
RCLKn
RTIPn
RDn
CVn
1
2
3
1
Figure-9 B8ZS Excessive Zeros
2
4
3
5
Ω
or
17
8 consecutive zeros
4
5
-0.2
-0.4
-0.6
1.2
0.8
0.6
0.4
0.2
1
0
0.00
-0.20
0.80
1.00
0.60
0.40
0.20
1.20
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
0
Figure-10 DSX-1 Waveform Template
Figure-11 CEPT Waveform Template
-300
-200
6
250
7
Excessive zeros detected
-100
8
500
Time (ns)
Time (ns)
0
9
6
750
7
100
September 22, 2005
8
200
1000
300
1250