82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 28

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-16 Expanded (Indirect Address Mode) Register List
Hex Serial Interface A7-A1 Parallel Interface A7-A0
0C
0D
1C
1D
IDT82V2044
0A
0B
0E
0F
1A
1B
1E
1F
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
Programming Information
XX00000
XX00001
XX00010
XX00011
XX00100
XX00101
XX00110
XX00111
XX01000
XX01001
XX01010
XX01011
XX01100
XX01101
XX01110
XX01111
XX10000
XX10001
XX10010
XX10011
XX10100
XX10101
XX10110
XX10111
XX11000
XX11001
XX11010
XX11011
XX11100
XX11101
XX11110
XX11111
Address
XXX00000
XXX00001
XXX00010
XXX00011
XXX00100
XXX00101
XXX00110
XXX00111
XXX01000
XXX01001
XXX01010
XXX01011
XXX01100
XXX01101
XXX01110
XXX01111
XXX10000
XXX10001
XXX10010
XXX10011
XXX10100
XXX10101
XXX10110
XXX10111
XXX11000
XXX11001
XXX11010
XXX11011
XXX11100
XXX11101
XXX11110
XXX11111
Register
e-CODE
e-RPDN
e-CODV
e-EQUA
e-TPDN
e-CZER
e-LBCF
e-LBAC
e-LBDC
e-LBGS
e-LBGE
e-SING
e-CRS
e-LBM
e-LBS
ADDP
e-LBI
R/W
R/W Single Rail Mode Setting Register
R/W Encoder/Decoder Selection Register
R/W Clock Recovery Enable/Disable Register
R/W Receiver n Powerdown Enable/Disable Register
R/W Transmitter n Powerdown Enable/Disable Register
R/W Consecutive Zero Detect Enable/Disable Register
R/W Code Violation Detect Enable/Disable Register
R/W Enable Equalizer Enable/Disable Register
R/W Inband Loopback Configuration Register
R/W Inband Loopback Activation Code Register
R/W Inband Loopback Deactivation Code Register
R/W Inband Loopback Interrupt Mask Register
R/W Inband Loopback Activate/Deactivate Code Generator Selection Register
R/W Inband Loopback Activate/Deactivate Code Generator Enable Register
R/W
R
R
28
Inband Loopback Code Receive Status Register
Inband Loopback Interrupt Status Register
Address pointer control register for switching between primary register bank
and expanded register bank
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Test
Explanation
September 22, 2005