82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 8

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
SDO/RDY/ACK
TS0/SDI/WR/
IDT82V2044
LP3/D3/AD3
LP2/D2/AD2
LP1/D1/AD1
LP0/D0/AD0
Pin Description
D7/AD7
D6/AD6
D5/AD5
D4/AD4
Name
INT
DS
High-Z
Open
Drain
Type
I/O
O
O
I
TQFP144
84
83
82
28
27
26
25
24
23
22
21
Pin No.
PBGA160
K14
K13
J14
K1
H2
H3
G2
J1
J2
J3
J4
TS0: Template Select 0
In hardware control mode, the signal on this pin is the least significant bit for the transmit template select.
Refer to
SDI: Serial Data Input
In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on the rising
edges of SCLK.
WR: Write Strobe (Active Low)
In parallel Intel host mode, this pin is active low during write operation. The data on D[7:0] (in non-multi-
plexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges of WR.
DS: Data Strobe (Active Low)
In parallel Motorola host mode, this pin is active low. During a write operation (R/W = 0), the data on D[7:0]
(in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges
of DS. During a read operation (R/W = 1), the data is driven to D[7:0] (in non-multiplexed mode) or AD[7:0]
(in multiplexed mode) by the device on the rising edges of DS.
In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus
A[4:0] are latched into the device on the falling edges of DS.
SDO: Serial Data Output
In serial host mode, the data is output on this pin. In serial write operation, SDO is always in high-Z. In
serial read operation, SDO is in high-Z only when SDI is in address/command byte. Data on pin SDO is
clocked out of the device on the falling edges of SCLK if pin CLKE is high, or on the rising edges of SCLK
if pin CLKE is low.
RDY: Ready Output
In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed,
while low reports the host must insert wait states.
ACK: Acknowledge Output (Active Low)
In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write operation.
INT: Interrupt (Active Low)
This is the open drain, active low interrupt output. Four sources may cause the interrupt. Refer to
Interrupt Handling
LPn: Loopback Select 3~0
In hardware control mode, pin LPn configures the corresponding channel in different loopback mode, as
follows:
Refer to
In hardware control mode, D4 to D7 should be tied to VDDIO/2.
Dn: Data Bus 7~0
In non-multiplexed host mode, these pins are the bi-directional data bus.
ADn: Address/Data Bus 7~0
In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.
In serial host mode, these pins should be grounded.
2.5.1 Waveform Shaper
2.13 Loopback Mode
VDDIO/2
High
LPn
Low
for details.
8
for details.
for details.
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Loopback Configuration
Description
Remote Loopback
Analog Loopback
No loopback
September 22, 2005
2.20