82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 6

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
IDT82V2044
Pin Description
MODE2
MODE1
RCLK0
RCLK1
RCLK2
RCLK3
MCLK
Name
LOS0
LOS1
LOS2
LOS3
(Pulled to
VDDIO/2)
High-Z
Type
O
O
I
I
I
TQFP144
39
32
78
71
10
42
35
75
68
11
43
Pin No.
PBGA160
M14
K12
K11
P14
M1
P1
E1
K4
K3
E2
K2
RCLKn: Receive Clock for Channel 0~3
In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn. The
received data are clocked out of the device on the rising edges of RCLKn if pin CLKE is high, or on falling
edges of RCLKn if pin CLKE is low.
In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with
RDPn and RDNn. The clock is recovered from the signal on RCLKn.
If Receiver n is powered down, the corresponding RCLKn is in high-Z.
MCLK: Master Clock
This is an independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048 MHz
(for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.
In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse (Data
Recovery mode). When MCLK is low, all the receivers are powered down, and the output pins RCLKn,
RDPn and RDNn are switched to high-Z.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn pin
description for details).
NOTE: Wait state generation via RDY/ACK is not available if MCLK is not provided.
LOSn: Loss of Signal Output for Channel 0~3
A high level on this pin indicates the loss of signal when there is no transition over a specified period of
time or no enough ones density in the received signal. The transition will return to low automatically when
there is enough transitions over a specified period of time with a certain ones density in the received sig-
nal. The LOS assertion and desertion criteria are described in
MODE2: Control Mode Select 2
The signal on this pin determines which control mode is selected to control the device:
Hardware control pins include MODE[2:0], TS[2:0], LP[3:0], CODE, CLKE, JAS and OE.
Serial host Interface pins include CS, SCLK, SDI, SDO and INT.
Parallel host Interface pins include CS, A[4:0], D[7:0], WR/DS, RD/R/W, ALE/AS, INT and RDY/ACK. The
device supports multiple parallel host interface as follows (refer to MODE1 and MODE0 pin descriptions
below for details):
MODE1: Control Mode Select 1
In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin
is low, and operates with multiplexed address and data bus when this pin is high.
In serial host mode or hardware mode, this pin should be grounded.
MODE[2:0]
Hardware/Host Control Interface
100
101
110
111
VDDIO/2
MODE2
High
Low
6
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Non-multiplexed Motorola Interface
Non-multiplexed Intel Interface
Multiplexed Motorola Interface
Multiplexed Intel Interface
Description
Host Interface
Parallel Host Interface
Serial Host Interface
Control Interface
Hardware Mode
2.4.4 Loss of Signal (LOS)
September 22, 2005
Detection.