TXC-06880BIOG Transwitch Corporation, TXC-06880BIOG Datasheet - Page 91
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TXC-06880BIOG
Manufacturer Part Number
TXC-06880BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet
1.TXC-06880BIOG.pdf
(122 pages)
Specifications of TXC-06880BIOG
Operating Supply Voltage (typ)
1.8/3.3V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TXC-06880BIOG
Manufacturer:
SAMWHA
Quantity:
34 000
243C
2500
2504
2508
2540
2544
2548
PRELIMINARY TXC-06880-MB, Ed. 4
February 2005
(hex)
Addr
RC
RC
RO
RC
RO
RC
RO
RW
RO
RW
RO
RW
RO
Mode
31-0
15-0
31-16
15-0
31-16
15-0
31-16
0
31-1
15-0
31-16
15-0
31-16
range
Bit
value after
00000000
0000
0000
0000
0000
0000
0000
0
0
FFFF
FFFF
FFFF
FFFF
Egress FIFO Packet Drop Counter for Port 2 to Port 14
Default
reset
- Memory Maps and Bit Descriptions -
Egress FIFO Packet Drop Counter Port 15: The Egress FIFO Packet
Drop Counter counts dropped packets for either of the following
conditions: (a) Start of Packet and End of Packet in the same word (b)
Assertion of the SPI-3 Error pin after a start of packet has been received.
(c) An overflow occurred in the Egress FIFO. Packets are dropped in
store and forward mode only (Egress FIFO Mode = 0). Clear on Read.
Egress FIFO Full Status Per Port: Indication of Egress FIFO for all 16
ports. When 1, indicates the FIFO Full state. Clear on Read.
Reserved
Egress FIFO Disabled Error Status Per Port: Indication of Egress
FIFO Error when a disabled port (done through configuration register
Egress FIFO PHY/Port Enable) receives packet data from the SPI-3
interface. The packet data is discarded. When 1, indicates the
occurrence of the error. Clear on Read.
Reserved
Egress FIFO Start of Packet Error Status Per Port: Indication of
Egress FIFO Start of Packet Error. The error status is indicated on the
reception of packet data without the reception of a Start of Packet, after
an End of Packet. When 1, indicates the occurrence of the error. Clear
on Read.
Reserved
Egress FIFO Mode: This bit sets the FIFO mode for all Egress FIFOs.
0 - Store and Forward Mode
1 - Streaming Mode
Reserved
Egress FIFO Full Interrupt Mask Per Port: FIFO full interrupt mask for
the 16 Egress FIFOs (one per port). A 0 disables the mask and an
interrupt will be generated when the appropriate FIFO becomes full. The
interrupt is cleared by reading the status register Egress FIFO Full
Status Per Port. If this bit is 1, no interrupt will be generated.
Reserved
Egress FIFO Disabled Error Interrupt Mask Per Port: Disabled
Egress FIFO Error interrupt mask for the 16 Egress FIFOs (one per
port). A 0 disables the mask and an interrupt will be generated when the
appropriate FIFO/Port is disabled and receives data for a write. The
interrupt is cleared by reading the status register Egress FIFO Disabled
Error Status. If this bit is 1, no interrupt will be generated.
Reserved
.
.
Description
Envoy-CE2 Device
DATA SHEET
TXC-06880
91 o f 12 2