TXC-06885BIOG Transwitch Corporation, TXC-06885BIOG Datasheet - Page 93

• Manufacturer Part Number: TXC-06885BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06885BIOG

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2010
2014
2018
201C
2040
PRELIMINARY TXC-06885-MB, Ed. 6A
February 2005
(hex)
Addr
RW
RO
RW
RO
RW
RO
RO
RC
RO
Mode
7-0
31-8
7-0
31-8
0
31-1
31-0
0
1
2
3
31-4
range
Bit
value after
00000000
00000000
1
0
0
0
0
0
0
Default
reset
- Memory Maps and Bit Descriptions -
SPI-3 Input PTPA Low Threshold: Input SPI-3 near full low threshold
for assertion of PTPA. Once the PTPA is de-asserted because the
Egress FIFO reached the SPI-3 high threshold (SIPHT), PTPA will be
asserted when the Egress FIFO reaches the PTPA low threshold. This
allows for a hysteresis in the PTPA signal. The threshold is in words (8
bytes). Programmable values are 1 to 255 which corresponds to
threshold values of 8 to 2040, in 8 byte increments.
Reserved
SPI-3 Input PTPA High Threshold: Input SPI-3 near full high threshold
for de-assertion of PTPA. The high threshold is the fullness level in
words (8 bytes), when reached by the Egress FIFO will de-assert PTPA.
Programmable values are 1 to 255 which corresponds to threshold
values of 8 to 2040, in 8 byte increments. The PTPA High Threshold
should be set to at least 3 times the chunk size being used in the
attached device (associated with ISPI flow).
Reserved
Reserved
Must be set to 0 for normal operation.
Reserved
Reserved
SPI-3 Input STPA Violation Status: Status bit indicating that the Link
Layer Device has violated the agreed upon STPA protocol. An indication
that the Link Layer device has sent more data than agreed upon
between the PHY and Link layer devices after the de-assertion of STPA.
This bit is only valid in PHY mode.
SPI-3 Input Parity Error Status: Status bit indicating occurrence of
Parity error across the SPI-3 Input Interface bus. Clear on Read.
SPI-3 Input Packet Error Status: Status bit indicating occurrence of
Packet error across the SPI-3 Input Interface indicated by the Error
signal. Clear on Read.
SPI-3 Input Start of Packet Error Status: Status bit indicating
occurrence of Start of Packet error across the SPI-3 Input Interface.
Clear on Read.
Reserved
Description
Envoy-CE4 Device
DATA SHEET
TXC-06885
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