TXC-06885BIOG Transwitch Corporation, TXC-06885BIOG Datasheet - Page 97

• Manufacturer Part Number: TXC-06885BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06885BIOG

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

247C
2500
2504
2508
2540
2544
2548
254C
PRELIMINARY TXC-06885-MB, Ed. 6A
February 2005
(hex)
Addr
RC
RC
RC
RC
RW
RO
RW
RW
RW
Mode
31-0
31-0
31-0
31-0
0
31-1
31-0
31-0
31-0
range
Bit
value after
00000000
00000000
00000000
00000000
0
0
FFFFFFFF Egress FIFO Full Interrupt Mask Per Port: FIFO full interrupt mask for
FFFFFFFF Egress FIFO Disabled Error Interrupt Mask Per Port: Disabled
FFFFFFFF Egress FIFO Start of Packet Error Interrupt Mask Per Port: Egress
Egress FIFO Packet Drop Counter for Port 2 to Port 30
Default
reset
- Memory Maps and Bit Descriptions -
Egress FIFO Packet Drop Counter Port 31: The Egress FIFO Packet
Drop Counter counts dropped packets for either of the following
conditions: (a) Start of Packet and End of Packet in the same word (b)
Assertion of the SPI-3 Error pin after a start of packet has been received.
(c) An overflow occurred in the Egress FIFO. Packets are dropped in
store and forward mode only (Egress FIFO Mode = 0). Clear on Read.
Egress FIFO Full Status Per Port: Indication of Egress FIFO for all 32
ports. When 1, indicates the FIFO Full state. Clear on Read.
Egress FIFO Disabled Error Status Per Port: Indication of Egress
FIFO Error when a disabled port (done through configuration register
Egress FIFO PHY/Port Enable) receives packet data from the SPI-3
interface. The packet data is discarded. When 1, indicates the
occurrence of the error. Clear on Read.
Egress FIFO Start of Packet Error Status Per Port: Indication of
Egress FIFO Start of Packet Error. The error status is indicated on the
reception of packet data without the reception of a Start of Packet, after
an End of Packet. When 1, indicates the occurrence of the error. Clear
on Read.
Egress FIFO Mode: This bit sets the FIFO mode for all Egress FIFOs.
0 - Store and Forward Mode
1 - Streaming Mode
Reserved
the 32 Egress FIFOs (one per port). A 0 disables the mask and an
interrupt will be generated when the appropriate FIFO becomes full. The
interrupt is cleared by reading the status register Egress FIFO Full
Status Per Port. If this bit is 1, no interrupt will be generated.
Egress FIFO Error interrupt mask for the 32 Egress FIFOs (one per
port). A 0 disables the mask and an interrupt will be generated when the
appropriate FIFO/Port is disabled and receives data for a write. The
interrupt is cleared by reading the status register Egress FIFO Disabled
Error Status. If this bit is 1, no interrupt will be generated.
FIFO Start of Packet Error interrupt mask for the 32 Egress FIFOs (one
per port). A 0 disables the mask. An interrupt will be generated when the
appropriate FIFO/Port receives consecutive End of Packets. The
interrupt is cleared by reading the status register Egress FIFO Start of
Packet Error Status. If this bit is 1, no interrupt will be generated.
.
.
Description
Envoy-CE4 Device
DATA SHEET
TXC-06885
97 o f 12 8