LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 59

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v
Flow of events for an insertion of a transmit packet:
1.
2.
3.
4.
5.
6.
7.
Reserved – Must be 0.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special
conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the
execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH Status
Register (EPHSR), and enabling of these sources can be done via the Control Register. The possible sources
are:
1.
2.
3.
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error
Enable)
EPH INT will only be cleared by the following methods:
1.
2.
3.
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2)
the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the
RCV DISCRD bit in the RCV register set. The RX_OVRN INT bit latches the condition for the purpose of
being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with
the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement of the
FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the
next allocation request is processed or allocation fails.
Disable the Transmitter
Remove and release any “transmit done” packets in the TX FIFO
Via polling or an interrupt driven event, determine status of TX IDLE INT bit and wait until this bit is
set. This will determine when the transmitter is truly done with all transmit events.
Remove and store (if any, in software) Packet numbers from the transmit FIFO. (These packets will
later be restored into the TX FIFO after the control frame is inserted into the front of the TX FIFO).
Enable Transmitter
En-queue packet into TX FIFO
En-queue rest of packets, if any, into TX FIFO (restore TX FIFO)
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low
and the specific reason will be reflected by the bits:
Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK
transition.
Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.
Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above (3.1
to 3.4).
3.1
3.2
3.3
3.4
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
DATASHEET
Page 59
Revision 1.0 (10-24-08)