TS81102G0VTP E2V, TS81102G0VTP Datasheet - Page 36

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TS81102G0VTP

Manufacturer Part Number
TS81102G0VTP
Description
Manufacturer
E2V
Datasheet

Specifications of TS81102G0VTP

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
-40C to 110C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Operation in DR/2
Mode
Figure 30. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500MHz (Full Speed) – Principle of Operation
Figure 31.
Note:
If the reset rising edge had occurred in the first allowed window (on the left), the reset would have been effective on the first
represented clock rising edge (first clock rising edge of the schematic, on the left of the edge represented with the arrow).
Figure 32. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full Speed) – Principle of Operation
36
Allowed for the
Sync_RESET
Times Zones
The clock edge to which the reset applies is the one identified by the arrow.
TS81102G0
reset
Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500 MHz (Full-speed) – Timings
Fs/2
Sync_RESET
Sync_RESET
Fs/2
Fs/2
In DR/2 mode, the DMUX input clock can run at up to 1 GHz in 1:8 ratio or 500 MHz in 1:4
ratio, since the DR/2 clock from the ADC is half the sampling frequency.
Both cases are described in the following timing diagrams.
2105C–BDC–11/03

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