ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet - Page 20

• Manufacturer Part Number: ADM6996L-AA-T-1
• Manufacturer: Lantiq

Specifications of ADM6996L-AA-T-1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.6.4
The smart squelch circuit is responsible for determining when valid data is present on the differential receive. The
ADM6996L/LX implements an intelligent receive squelch on the RXP/RXN differential inputs to ensure that
impulse noise on the receive inputs will not be mistaken for a valid signal. The squelch circuitry employs a
combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to
determine the validity of data on the twisted-pair inputs.
The signal at the start of the packet is checked by the analog squelch circuit and any pulses not exceeding the
squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is
overcome correctly, the opposite squelch level must then be exceeded within 150ns. Finally, the signal must
exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected.
Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder
of the circuitry that valid data is present.
Valid data is considered to be present until the squelch level has not been generated for a time longer than 200
ns, indicating the end of a packet. Once good data has been detected, the squelch levels are reduced to minimize
the effect of noise, causing premature end-of-packet detection. The receive squelch threshold level can be
lowered for use in longer cable applications. This is achieved by setting bit 10 of register address 11h.
3.7
Carrier Sense (CRS) is asserted due to receive activity once valid data is detected via the smart squelch function.
For 10 Mbits/s half duplex operation, CRS is asserted during either packet transmission or reception. For 10
Mbits/s full duplex and repeater mode operations, the CRS is asserted only due to receive activity.
3.8
The jabber function monitors the ADM6996L/LX output and disables the transmitter if it attempts to transmit a
longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled.
Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is
asserted. This signal has to be de-asserted for approximately 256 ms (the un-jab time) before the jabber function
re-enables the transmit outputs. The jabber function can be disabled by programming bit 4 of register address 10h
to high.
3.9
A link pulse is used to check he integrity of the connection with the remote end. If valid link pulses are not received,
the link detector disables the 10Base-T twisted-pair transmitter, receiver, and collision detection functions.
The link pulse generator produces pulses as defined in IEEE 802.3 10Base-T standard. Each link pulse is
nominally 100ns in duration and is transmitted every 16 ms, in the absence of transmit data.
3.10
The ADM6996L/LX’s 10Base-T transceiver module incorporates an “automatic link polarity detection circuit”. The
inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive
packets are received with inverted end-of-packet pulses. If the input polarity is reversed, the error condition will be
automatically corrected and reported in bit 5 of register 10h.
3.11
The ADM6996L/LX implements a clock synthesizer that generates all the reference clocks needed from a single
external frequency source. The clock source must be a TTL level signal at 25 MHz +/- 50ppm
Data Sheet
Smart Squelch
Carrier Sense
Jabber Function
Link Test Function
Automatic Link Polarity Detection
Clock Synthesizer
20
Function Description
Rev. 1.13, 2005-11-22
ADM6996L/LX
Data Sheet