ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet - Page 17

• Manufacturer Part Number: ADM6996L-AA-T-1
• Manufacturer: Lantiq

Specifications of ADM6996L-AA-T-1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.4.1
A high performance A/D converter with a 125 MHz sampling rate converts signals received on the RXP/RXN pins
to 6 bits data streams. It possess an auto-gain-control capability that will further improve receive performance
especially under long cabling or harsh detrimental signal integrity. Due to high pass characteristic on a
transformer, a built in base-line-wander correcting circuit will be cancelled out and its DC level restored.
3.4.2
All digital design is especially immune to noise environments and achieves better correlation between production
and system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates for line loss induced from
twisted pairs and tracks a far end clock at 125M samples per second. Adaptive Equalizer’s implemented with Feed
forward and Decision Feedback techniques meet the requirement of BER with less than 10-12 for transmission on
a CAT5 twisted pair cable ranging from 0 to 120 meters.
3.4.3
The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to the 4B/5B code group’s
boundary.
3.4.4
The de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and
locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving
synchronization, the incoming data is XORed by the deciphering LFSR and de-scrambled.
In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data
that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the de-scrambler the hold timer starts a 722 micro second
countdown. Upon detection of sufficient idle symbols within the 722 micro sec. period, the hold timer will reset and
begin a new countdown. This monitoring operation will continue indefinitely given an operating network connection
operating with good signal integrity. If the link state monitor does not recognize sufficient unscrambled idle symbols
within the 722 micro second period, the de-scrambler will be forced out of the current state of synchronization and
reset in order to re-acquire synchronization.
3.4.5
The symbol alignment circuit in the ADM6996L/LX determines code word alignment by recognizing the /J/K
delimiter pair. This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000
10001) is detected, subsequent data is aligned on a fixed boundary.
3.4.6
The symbol decoder functions is a look-up table that translates incoming 5B symbols into 4B nibbles. The symbol
decoder first detects the /J/K symbol pair preceded by idle symbols and replaces the symbol with a MAC preamble.
All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet.
This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD).
The translated data is presented on the internal RXD[3:0] signal lines where RXD[0] represents the least
significant bit of the translated nibble.
3.4.7
The valid data signal (RXDV) indicates that recovered and decoded nibbles are being presented on the internal
RXD[3:0] synchronous receive clock, RXCLK. RXDV is asserted when the first nibble of a translated /J/K is ready
for transfer over the internal MII. It remains active until either the /T/R delimiter is recognized, link test indicates
failure, or no signal is detected. On any of these conditions, RXDV is de-asserted.
Data Sheet
A/D Converter
Adaptive Equalizer and timing Recovery Module
NRZI/NRZ and Serial/Parallel Decoder
Data De-scrambling
Symbol Alignment
Symbol Decoding
Valid Data Signal
17
Function Description
Rev. 1.13, 2005-11-22
ADM6996L/LX
Data Sheet