MCZ33780EG Freescale, MCZ33780EG Datasheet - Page 13

• Manufacturer Part Number: MCZ33780EG
• Manufacturer: Freescale

Specifications of MCZ33780EG

• Operating Supply Voltage (typ): 5/12/15/18/24V
• Operating Supply Voltage (min): 4.75/9V
• Operating Supply Voltage (max): 5.25/25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

distributed system. It contains both protocol generators and
physical interfaces to allow an MCU to communicate with
devices on the bus using only a simple SPI interface. Two
differential busses are provided.
presence of an open circuit. This is immediate and no
interruption is caused by the open circuit. The differential
outputs have reduced electromagnetic radiation and
susceptibility.
connected between the two bus wires and capacitors
between the bus wires and ground. Because the voltage
change on either of the bus wires to ground is only 1/2 the
Table 5. High-Side and Low-Side Typical Voltages (Voltage Relative to Ground)
RESET (RST)
known state as indicated in the section entitled
Descriptions.
CHIP SELECT (CS)
ground. When high, the SPI signals are ignored. The SPI
transaction is signaled as completed when this signal returns
high.
INTERRUPT (INT)
condition occurs. It contains an internal current pull-up
source so that it will remain high when not active. The output
is open-drain so that it can be ORed together with other open-
drain outputs so that this IC or any of the others can assert an
interrupt.
MASTER OUT/SLAVE IN (MOSI)
sampled on the positive (rising) edge of SCLK.
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
The 33780 is intended to be used as a master device in a
Using a loop-back wire allows operation of the bus in the
The equivalent bus capacitance consists of capacitors
When pulled low, this will reset all internal registers to a
This input is used to select the SPI port when pulled to
This output will be asserted ow when an enabled interrupt
This is the SPI data input to the device. This data is
Vmid = V
IDLE
0
SUP
/ 2.
Vmid - 2.25
Low Side
HIGH
(18)
FUNCTIONAL DESCRIPTIONS
Vmid - 0.75
FUNCTIONAL PIN DESCRIPTIONS
Register and Bit
LOW
(18)
INTRODUCTION
IDLE
V
amount of change between the two bus wires, the
capacitance to ground only conducts half as much current as
it would if connected directly across the bus. The equivalent
bus capacitance of a capacitor to ground from the bus wires
is one half of the actual amount of the capacitor. The amount
of capacitance from either bus wire to ground should be kept
the same in order to achieve the lowest radiated EMI energy.
The 4.7 nF capacitors required between the bus wires and
ground result in an equivalent of 2.35 nF of capacitance
across the bus as seen by either bus wire.
(LS) is the bus wire that is the most negative and high side
(HS) is the bus wire that is the most positive.
the bus waveforms in normal operation.
SERIAL CLOCK (SCLK)
controls the clocking of data to the device and data read from
the device.
MASTER IN/SLAVE OUT (MISO)
MCU). Data changes on the negative (falling) transition of the
SCLK.
CLOCK (CLK)
be 4.0 MHz.
GROUND (GND)
POWER SOURCE (VCC)
be bypassed with a small capacitor to ground (0.01-0.1
LOW-SIDE BUS (DnL)
D1L They comprise the low-side differential output signal of
SUP
Table 5
This is the clock signal from the SPI master device. It
This is the SPI data from the device to the SPI master (the
This is the main clock source for the internal logic. It must
Ground source for both logic and DBUS return.
Logic power source. Nominal value is +5.0 V. This should
There are two independent LOW-SIDE outputs, D0L and
shows the voltages used for operation. Low side
Vmid + 2.25
High Side
HIGH
(18)
FUNCTIONAL DESCRIPTIONS
Vmid + 0.75
INTRODUCTION
Figure 5
LOW
(18)
shows
33780
µ
F)
13