MCZ33780EG Freescale, MCZ33780EG Datasheet - Page 20

• Manufacturer Part Number: MCZ33780EG
• Manufacturer: Freescale

Specifications of MCZ33780EG

• Operating Supply Voltage (typ): 5/12/15/18/24V
• Operating Supply Voltage (min): 4.75/9V
• Operating Supply Voltage (max): 5.25/25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

20
value to DnH and/or DnL. When the minimum inter-frame
delay has been satisfied, the DSIF pin will go low, indicating
the start of a new transfer frame.
(DSIF), a data signal (DSIS), and a data return (DSIR) signal.
These are signals internal to the IC associated with the
prData is shifted out of DSIS (MSB first) and shifted into DSIR
at the same time. As a message is received, it is stored bit-
by-bit into the next available receive FIFO location. For each
data value in the receive FIFO, there is a one-bit status flag
to indicate whether or not there was a CRC error while
receiving the data. At the end of a DBUS transfer (and after
the CRC error status is stable), the RFNEn flag is set (if it was
not already) to indicate there is data in the receive FIFO to be
read.
DATA RATE
by the system clock (CLK) and the programmable clock
divider. (The Clock Divider ratio n is defined in
the system clock (CLK) and the DnOFFSETL/H register
programming. Note the programmable clock divider does not
control the data rate in Spread Spectrum mode. Refer to
Register and Bit Descriptions
offset and the data rate for f
computed using the following formula:
--------------------------------------------------------------------------
-- Calculates the 4-bit CRC (x^4 + 1) serially for 8 to 16 bits of data.
33780
Table 7. Data Rate versus OFFSET (Spread Spectrum)
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DBUS Driver/Receiver communications involve a frame
In non-spread spectrum mode, the data rate is determined
In spread spectrum mode, the data rate is determined by
The following table gives the correspondence between the
For other clock frequencies, the data rate can be
HEX
3F
7A
9F
00
Data Rate = (f
OFFSET
DEC
122
159
Data Rate = f
63
0
CLK
/ 33) * (1 + OFFSET / 512)
CLK
section for details.
CLK
= 4.0 MHz.
/ (27 * n)
Data Rate
121.2
136.1
150.1
158.9
kHz
Table
10.)
CRC GENERATION / CHECKING
CRC value is computed and serially sent as the next n bits
after the LSB of the data. The CRC length, polynomial, and
initial seed are determined by the CRCLEN[3:0],
CRCPOLY[7:0], and CRCSEED[7:0] control register fields.
The message, including the CRC bits, is passed along to a
remote peripheral, which computes a separate CRC value as
the message data is received. If this computed CRC does not
agree with the CRC value received in the message, the
peripheral device considers the message invalid.
was computed in the peripheral device that is responding. As
the message is received, a separate 0- to 8-bit CRC value is
computed and is compared with the CRC value in the
received message. If these values do not agree, the message
is considered invalid and the ERn status bits in the D01STAT
register are set as the receive data is transferred into the
receive data buffer.
data pattern received will be all zeros with a CRC value of 0,
which may be detected as a CRC error depending on the
values of CRCLEN[3:0], CRCPOLY[7:0], and
CRCSEED[7:0]. On the other hand, if a remote peripheral is
attached and responds with all zeros with a CRC value of
1010, this may be detected as a non-error condition.
CRC COMPUTATION
value, or seed, of CRCSEED[7:0] and a programmable
polynomial of CRCPOLY[7:0].
description of the CRC algorithm for the DBUS standard 4-bit
CRC with its initial value of 1010. A seed value is chosen so
that a zero data value will generate a CRC value of 1010. A
block diagram of the default CRC calculation is shown in
Figure
Whenever a message is sent on the DBUS, a 0- to 8-bit
Messages received include a 0- to 8-bit CRC value, which
When no remote peripheral responds to a message, the
The CRC algorithm uses a programmable initialization
17.
Analog Integrated Circuit Device Data
Figure 16
Freescale Semiconductor
is a VHDL