SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 22

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si3050 + Si3011
Schematic" on page 17, to the line-side device and
returned across the same path. In this digital loopback
mode, the 0.9 dB attenuation and filter group delays
also exist.
The PCM analog loopback mode extends the signal
path of the analog loopback mode. In this mode, an
analog signal is driven from the line into the line-side
device. This analog signal is converted to digital data
and then passed across the communications link to the
system-side device. The data passes through the
receive filter, through the transmit filter, and is then
passed across the communications link and sent back
out onto the line as an analog signal. Set the PCML bit
(Register 33, bit 7) to enable this mode.
With the final testing mode, internal analog loopback,
the system can test the operation of the transmit and
receive paths on the line-side device and the external
components in the "2. Typical Application Schematic"
on page 17. The host provides a digital test waveform
on DRX. Data passes across the isolation barrier, is
transmitted to and received from the line, passes back
across the isolation barrier, and is presented to the host
on DTX. Clear the HBE bit (Register 2, bit 1) to enable
this mode.
When the HBE bit is cleared, it produces a dc offset that
affects the signal swing of the transmit signal. Silicon
Laboratories recommends that the transmit signal be
12 dB lower than normal transmit levels. A lower level
eliminates clipping from the dc offset that results from
disabling the hybrid. It is assumed in this test that the
line ac impedance is nominally 600 
Note: All test modes are mutually exclusive. If more than one
5.8. Exception Handling
The Si3050 can determine if an error occurs during
operation. Through the secondary frames of the serial
link, the controlling DSP can read several status bits.
The bit of highest importance is the frame detect bit
(FDT, Register 12, bit 6) which indicates that the
system-side (Si3050) and line-side (Si3011) devices are
communicating. During normal operation, the FDT bit
can be checked before reading the bits that indicate
information about the line side. If FDT is not set, the
following bits related to the line side are invalid—RDT,
RDTN,
LVS[7:0], LCS2[7:0], ROV, BTD, DOD, and OVL; the
RGDT operation is also non-functional.
Following powerup and reset, the FDT bit is not set
because the PDL bit (Register 6 bit 4) defaults to 1. In
this state, the ISOcap is not operating and no
information about the line side can be determined. The
22
test mode is enabled concurrently, the results are
unpredictable.
RDTP,
LCS[4:0],
LSID[1:0],
REVB[3:0],
Rev. 1.11
user must provide a valid PCLK and FSYNC to the
system and clear the PDL bit to activate the ISOcap
link. Communication with the line-side device takes less
than 10 ms to establish.
5.9. Revision Identification
The Si3050 provides information to determine the
revision of the Si3050 and/or the Si3011. The REVA[3:0]
bits (Register 11) identify the revision of the Si3050,
where 0101b denotes revision E. The REVB[3:0] bits
(Register 13) identify the revision of the line-side device,
where 0110b denotes revision F.
5.10. Transmit/Receive Full-Scale Level
The Si3050 supports programmable maximum transmit
and receive levels. The default signal level supported by
the Si3050 is 0 dBm into a 600  load. The
Si3050+Si3011 chipset supports an enhanced full-scale
mode that can be enabled by setting the FULL2 bit in
Register 30. With FULL2 = 1, the full-scale signal level
increases to +6.0 dBm into a 600  load or 1.5 dBV into
all reference impedances. The full-scale and enhanced
full-scale modes provide the ability to trade off TX power
and TX distortion for a peak signal. By using the
programmable digital gain registers in conjunction with
the enhanced full-scale signal level mode, a specific
power level (+3.2 dBm for example) can be achieved
across all ACT settings.
5.11. Parallel Handset Detection
The Si3050 can detect a parallel handset going
off-hook. When the Si3050 is off-hook, the loop current
can be monitored with the LCS or LCS2 bits. A
significant drop in loop current signals a parallel handset
going off-hook. If a parallel handset going off-hook
causes the loop current to drop to 0, the LCS and LCS2
bits will read all 0s. Additionally, the Drop-Out Detect
(DOD) bit will fire (and generate an interrupt if the
DODM bit is set) indicating that the line-derived power
supply has collapsed.
The LVS bits also can be read when on- or off-hook to
determine the line voltage. Significant drops in line
voltage can signal a parallel handset. For the Si3050 to
operate in parallel with another handset, the parallel
handset must have a sufficiently high dc termination to
support two off-hook DAAs on the same line. Improved
parallel handset operation can be achieved by changing
the dc impedance from 50  to 800 .