SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 52

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si3050 + Si3011
5.45. Receive SC Channel
:
These bits are defined as follows:
CIR6: Reserved
CIR5: Reserved
CIR4: ONHM
CIR3: TGDE
CIR2: RG
CIR1: OH
Data that is received must be consistent and match for at least two consecutive frames to be considered valid.
When a new command or status is communicated via the C/I bits, the data must be sent for at least two
consecutive frames to be recognized by the Si3050. The following steps describe the protocol of how C/I bits are
stored, detected, and validated. This is illustrated in Figure 47.
1. The current state of the C/I bits are stored in a primary register P. If the received C/I bits are identical to this
2. Upon receipt of an SC channel with C/I bits that differ from the current state, these new C/I bits are immediately
3. The C/I bits in the SC channel received in the frame immediately after the SC channel just stored in S are
52
MSB
current state, no action is taken.
latched into a secondary register S.
compared with the C/I bits in the S register.
a. If the C/I bits in these two channels are identical, then the C/I bits in the S register are loaded into the P
b. If a set of C/I bits is latched into the S register and the subsequent set of C/I bits received does not match
c. If the C/I bits in the SC channel received immediately after the SC channel just stored in S do not match the
register and are considered a valid change of C/I bits. The Si3050 then responds accordingly to the changed
C/I bits.
either the S or P registers, then the newly received set of C/I bits are latched into the S register. This
continues to occur as long as the subsequent set of C/I bits received differs from the C/I bits in the S and
P registers.
C/I bits stored in S, but DO match the C/I bits stored in P, then the single set of C/I bits stored in the S latch
are invalidated, and the current state of the C/I bits in P remains unchanged.
CIR6
7
CIR5
6
CIR4
5
CIR3
4
Rev. 1.11
C/I Bits
CIR2
3
CIR1
2
MR
1
MX
0
LSB