HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet - Page 13

• Manufacturer Part Number: HBLXT9781HC.C4
• Manufacturer: Intel

Specifications of HBLXT9781HC.C4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761.
9761 Pin#
where X is the register number (0-32) and Y is the bit number (0-15).
Table 1. LXT97x1 RMII Signal Descriptions
PQFP
92
66
69
59
60
46
47
23
24
14
17
65
58
45
22
13
62
61
55
54
7
8
–
–
6
–
–
PQFP
92
66
69
59
60
46
47
39
40
30
33
23
24
14
17
65
58
45
38
29
22
13
62
61
55
54
7
8
6
9781 Pin#
PBGA
Y15
W7
W4
W3
G2
V7
V4
T2
T3
P3
P4
F4
D3
D4
Y5
T1
P1
F3
D2
U7
U6
Y2
V2
L3
L4
J3
J4
L2
J2
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
REFCLK
TXD0_0
TXD0_1
TXD1_0
TXD1_1
TXD2_0
TXD2_1
TXD3_0
TXD3_1
TXD4_0
TXD4_1
TXD5_0
TXD5_1
TXD6_0
TXD6_1
TXD7_0
TXD7_1
TXEN0
TXEN1
TXEN2
TXEN3
TXEN4
TXEN5
TXEN6
TXEN7
RXD0_0
RXD0_1
RXD1_0
RXD1_1
Symbol
RMII Data Interface Pins
Type
O
O
I
I
I
I
I
I
I
I
I
I
1
Reference Clock. 50 MHz RMII reference clock is required
at this pin. The LXT97x1 samples RMII inputs on the rising
edge of REFCLK, and drives RMII outputs on the falling
edge.
Transmit Data - Port 0. Inputs containing 2-bit parallel di-bits
to be transmitted from port 0 are clocked in synchronously to
REFCLK.
Transmit Data - Port 1. Inputs containing 2-bit parallel di-bits
to be transmitted from port 1 are clocked in synchronously to
REFCLK.
Transmit Data - Port 2. Inputs containing 2-bit parallel di-bits
to be transmitted from port 2 are clocked in synchronously to
REFCLK.
Transmit Data - Port 3. Inputs containing 2-bit parallel di-bits
to be transmitted from port 3 are clocked in synchronously to
REFCLK.
Transmit Data - Port 4. Inputs containing 2-bit parallel di-bits
to be transmitted from port 4 are clocked in synchronously to
REFCLK.
Transmit Data - Port 5. Inputs containing 2-bit parallel di-bits
to be transmitted from port 5 are clocked in synchronously to
REFCLK.
Transmit Data - Port 6. Inputs containing 2-bit parallel di-bits
to be transmitted from port 6 are clocked in synchronously to
REFCLK.
Transmit Data - Port 7. Inputs containing 2-bit parallel di-bits
to be transmitted from port 7 are clocked in synchronously to
REFCLK.
Transmit Enable - Ports 0 - 7. Active High input enables
respective port transmitter. This signal must be synchronous
to the REFCLK.
Receive Data - Port 0. Receive data signals (2-bit parallel di-
bits) are driven synchronously to REFCLK.
Receive Data - Port 1. Receive data signals (2-bit parallel di-
bits) are driven synchronously to REFCLK.
Signal Description
2, 3
13