HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet - Page 21

• Manufacturer Part Number: HBLXT9781HC.C4
• Manufacturer: Intel

Specifications of HBLXT9781HC.C4

• Lead Free Status / RoHS Status: Not Compliant

2.0
2.1
2.1.1
2.1.2
Datasheet
Functional Description
Introduction
The LXT9781 is an eight-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and 100
Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT9781
provides a Reduced MII (RMII) for each individual network port to interface with multiple 10/100
MACs. Each port can directly drive either a 100BASE-TX line (up to 100 meters) or a 10BASE-T
line (up to 185 meters). The LXT9781 also supports 100BASE-FX operation via a Pseudo-ECL
(PECL) interface. The LXT9761 offers the same features and functionality in a six-port device.
This data sheet uses the singular designation “LXT97x1” to refer to both devices.
OSP™ Architecture
Intel's LXT97x1 incorporates high-efficiency Optimal Signal Processing™ design techniques,
combining the best properties of digital and analog signal processing to produce a truly optimal
device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result
is improved receiver noise and cross-talk performance.
The OSP architecture also requires substantially less computational logic than traditional DSP-
based designs. This lowers power consumption and also reduces the logic switching noise
generated by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a
considerable source of EMI generated on the device’s power supplies.
The OSP-based LXT97x1 provides improved data recovery, EMI performance and power
consumption.
Comprehensive Functionality
The LXT97x1 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device
also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
On power-up, the LXT97x1 reads its configuration pins to check for forced operation settings. If
not configured for forced operation, each port uses auto-negotiation/parallel detection to
automatically determine line operating conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT97x1 will auto-negotiate with it using Fast Link Pulse (FLP)
Bursts. If the PHY partner does not support auto-negotiation, the LXT97x1 will automatically
detect the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set
its operating conditions accordingly.
The LXT97x1 provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
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