FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 21

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Table 8.
Note: Pull-up/pull-down resistors of 10k Ohms can be implemented if LEDs are not used in the design.
Table 8
Intel
PBGA
Pin#
D1
D2
C2
H1
H8
H7
C1
E8
B1
E6
F7
F8
®
LXT971A Transceiver Configuration and LED Driver Signal Descriptions
lists signal descriptions of the LXT971A Transceiver configuration and LED driver pins.
LQFP
Pin#
17
33
32
39
38
37
36
5
6
4
1
2
REFCLK/XI
LED/CFG1
LED/CFG2
LED/CFG3
PWRDWN
TxSLEW0
TxSLEW1
RESET_L
Symbol
PAUSE
SLEEP
RBIAS
XO
Intel
®
Type
I and
I/O
AI
LXT971A Single-Port 10/100 Mbps PHY Transceiver
O
I
I
I
I
I
Tx Output Slew Controls 0 and 1.
These pins select the TX output slew rate (rise and fall time)
as follows:
Reset.
This active Low input is ORed with the control register Reset
bit (Register bit 0.15). The LXT971A Transceiver reset cycle
is extended to 258 μs (nominal) after reset is de-asserted.
Reference Current Bias.
This pin provides bias current for the internal circuitry. Must
be tied to ground through a 22.1 kΩ, 1% resistor.
Pause.
When set High, the LXT971ATransceiver advertises Pause
capabilities during auto-negotiation.
Sleep.
When set High, this pin enables the LXT971A Transceiver to
go into a low-power sleep mode. The value of this pin can be
overridden by Register bit 16.6 when in managed mode.
Power Down.
When set High, this pin puts the LXT971A Transceiver in a
power-down mode.
Reference Clock Input / Crystal Input and Crystal Output.
A 25 MHz crystal oscillator circuit can be connected across XI
and XO. A clock can also be used at XI.
For clock requirements, see
Requirements” on page 32
section.
LED Drivers 1-3.
These pins drive LED indicators. Each LED can display one
of several available status conditions as selected by the LED
Configuration Register. (For details, see
Configuration Register - Address 20, Hex 14” on page
Configuration Inputs 1-3.
These pins also provide initial configuration settings. (For
details, see
Intel® LXT971A Transceiver” on page
TxSLEW1
0
0
1
1
Table 12, “Hardware Configuration Settings for
TxSLEW0
0
1
0
1
Signal Description
in the Functional Description
Section 5.3.2, “Clock
Slew Rate (Rise and Fall Time)
37.)
Table 59, “LED
3.0 ns
3.4 ns
3.9 ns
4.4 ns
101.)
21