FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 87

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Figure 41. Intel
Table 43. Intel
RESET_L pulse width
RESET_L recovery delay
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
testing.
performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300 μ s before accessing the MDIO port.
®
®
LXT971A Transceiver RESET_L Pulse Width and Recovery Timing
LXT971A Transceiver RESET_L Pulse Width and Recovery Timing
Parameter
MDIO, and
RESET_L
so on
2
Symbol
Intel
t1
t2
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Min
10
–
Typ
–
1
Max
300
–
t1
Units
μ s
ns
t2
B3495-01
Test Conditions
–
–
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