FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 41

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

5.6
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
MII Operation
This section includes the following topics:
The LXT971A Transceiver implements the Media Independent Interface (MII) as defined by the
IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the
LXT971A Transceiver (TXD), and for passing data received from the line (RXD) to the MAC.
Each channel has its own clock, data bus, and control signals.
The following signals are used to pass received data to the MAC:
The following signals are used to transmit data from the MAC:
The LXT971A Transceiver supplies both clock signals as well as separate outputs for carrier sense
and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
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Section 5.6.1, “MII Clocks”
Section 5.6.2, “Transmit Enable”
Section 5.6.3, “Receive Data Valid”
Section 5.6.4, “Carrier Sense”
Section 5.6.5, “Error Signals”
Section 5.6.6, “Collision”
Section 5.6.7, “Loopback”
COL
CRS
RX_CLK
RX_DV
RX_ER
RXD[3:0]
TX_CLK
TX_EN
TX_ER
TXD[3:0]
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
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