FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 76

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FLLXT971ABC.A4

Manufacturer Part Number
FLLXT971ABC.A4
Description
Manufacturer
Intel
Datasheet

Specifications of FLLXT971ABC.A4

Lead Free Status / RoHS Status
Not Compliant

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Intel
7.2
76
Figure 28. Intel
Table 32. Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Timing Diagrams
RXD[3:0], RX_DV, RX_ER
RX_CLK High
RXD[3:0], RX_DV, RX_ER hold
from RX_CLK High
CRS asserted to RXD[3:0], RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
3. RX_ER is not shown in the figure.
testing.
rate. 100BASE-T bit time = 10
®
RXD[3:0]
®
RX_CLK
LXT971A Transceiver 100BASE-TX Receive Timing Parameters - 4B Mode
LXT971A Transceiver 100BASE-TX Receive Timing - 4B Mode
RX_DV
TPFI
CRS
COL
Parameter
0 ns
3
setup to
-8
s or 10 ns.
t4
t6
Sym
t1
t2
t3
t4
t5
t6
t7
Min
10
10
12
10
16
17
t3
3
250 ns
Typ
1
t5
t7
Max
t1
16
17
22
20
5
t2
B3491-02
Document Number: 249414-003
Units
Revision Date: June 18, 2004
BT
BT
BT
BT
BT
ns
ns
2
Test Conditions
Datasheet

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