PIC12LF1840T-I/MF Microchip Technology, PIC12LF1840T-I/MF Datasheet - Page 104
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/0/160077/dfn8_sml.jpg)
PIC12LF1840T-I/MF
Manufacturer Part Number
PIC12LF1840T-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840T-I/MF
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840T-I/MF
Manufacturer:
MICROCHIP
Quantity:
12 000
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PIC12(L)F1840
EXAMPLE 11-4:
DS41441B-page 104
; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
ERASING ONE ROW OF PROGRAM MEMORY
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
55h
EECON2
0AAh
EECON2
EECON1,WR
EECON1,WREN
INTCON,GIE
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Point to program memory
; Not configuration space
; Specify an erase operation
; Enable writes
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
; Any instructions here are ignored as processor
; halts to begin erase sequence
; Processor will stop here and wait for erase complete.
; after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
Preliminary
2011 Microchip Technology Inc.
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