PIC12LF1840T-I/MF Microchip Technology, PIC12LF1840T-I/MF Datasheet - Page 74
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/0/160077/dfn8_sml.jpg)
PIC12LF1840T-I/MF
Manufacturer Part Number
PIC12LF1840T-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840T-I/MF
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840T-I/MF
Manufacturer:
MICROCHIP
Quantity:
12 000
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PIC12(L)F1840
7.10
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset.
tions of these registers.
TABLE 7-3:
TABLE 7-4:
DS41441B-page 74
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
WDT Wake-up from Sleep
Brown-out Reset
Interrupt Wake-up from Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
STKOVF STKUNF RMCLR
0
0
0
0
u
u
u
u
u
u
1
u
2: If a Status bit is not implemented, that bit will be read as ‘0’.
Table 7-3
Determining the Cause of a Reset
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
0
0
0
0
u
u
u
u
u
u
u
1
and
RESET STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
Table 7-4
Condition
1
1
1
1
u
u
u
0
0
u
u
u
show the Reset condi-
RI
1
1
1
1
u
u
u
u
u
0
u
u
POR
0
0
0
u
u
u
u
u
u
u
u
u
Preliminary
BOR
x
x
x
0
u
u
u
u
u
u
u
u
TO
1
0
x
1
0
0
1
u
1
u
u
u
Program
PC + 1
Counter
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
PD
1
x
0
1
u
0
0
u
0
u
u
u
(1)
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
(2)
---1 1000
---u uuuu
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
Register
STATUS
2011 Microchip Technology Inc.
Condition
00-- 110x
uu-- 0uuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
Register
PCON
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