PIC12LF1840T-I/MF Microchip Technology, PIC12LF1840T-I/MF Datasheet - Page 212

7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano

PIC12LF1840T-I/MF

Manufacturer Part Number
PIC12LF1840T-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet

Specifications of PIC12LF1840T-I/MF

Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12LF1840T-I/MF
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC12(L)F1840
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 25-2
ule in Master mode.
interface module in Slave mode.
FIGURE 25-2:
DS41441B-page 212
2
C interface supports the following modes and
SDA
SCL
is a block diagram of the I
Figure 25-3
MSSP1 BLOCK DIAGRAM (I
SDA in
is a diagram of the I
Bus Collision
SCL in
2
C interface mod-
Read
MSb
Generate (SSP1CON2)
Address Match detect
Preliminary
Write collision detect
2
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock arbitration
C
Start bit detect,
Stop bit detect
Acknowledge
SSP1BUF
SSP1SR
2
C™ MASTER MODE)
LSb
Write
Clock
Shift
data bus
Internal
Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV
Reset SEN, PEN (SSP1CON2)
Set SSP1IF, BCL1IF
 2011 Microchip Technology Inc.
[SSP1M 3:0]
Baud rate
generator
(SSP1ADD)

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