PIC16F1828-E/SS Microchip Technology, PIC16F1828-E/SS Datasheet - Page 333

• Manufacturer Part Number: PIC16F1828-E/SS
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1828-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1824/1828
REGISTER 27-2:
TABLE 27-3:
DS41419B-page 332
ANSELA
ANSELC
CPSCON0
CPSCON1
INLVLA
INLVLB
INLVLC
INTCON
OPTION_REG
T1CON
TRISA
TRISB
TRISC
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module.
Note 1:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Note 1:
Name
U-0
(1)
—
(1)
PIC16F/LF1828 only.
These channels are only implemented on the PIC16F/LF1828.
INLVLC7
TMR1CS1 TMR1CS0
TRISC7
INLVLB7
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
If CPSON = 1:
WPUEN
CPSON
TRISB7
ANSC7
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7
GIE
—
—
—
—
These bits are ignored. No channel is selected.
U-0
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
1000 = channel 8, (CPS4)
1001 = channel 9, (CPS5)
1010 = channel 10, (CPS6)
1011 = channel 11, (CPS7)
1100 = Reserved. Do not use.
1111 = Reserved. Do not use.
•
•
•
—
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
(1)
(1)
INLVLC6
TRISC6
INLVLB6
INTEDG
CPSRM
TRISB6
ANSC6
PEIE
Bit 6
—
—
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
(1)
(1)
U-0
—
T1CKPS1
TMR0CS
INLVLA5
INLVLB5
INLVLC5
TMR0IE
TRISA5
TRISB5
TRISC5
Bit 5
—
—
—
—
(1)
(1)
(1)
(1)
T1CKPS0
U-0
INLVLC4
TMR0SE
INLVLA4
INLVLB4
Preliminary
TRISC4
—
TRISA4
TRISB4
ANSA4
INTE
Bit 4
—
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
CPSRNG1 CPSRNG0
T1OSCEN
CPSCH3
INLVLC3
INLVLA3
TRISC3
TRISA3
ANSC3
IOCIE
Bit 3
PSA
—
—
—
CPSCH<3:2>
(1)
CPSCH2
INLVLC2
INLVLA2
T1SYNC
TMR0IF
TRISA2
TRISC2
ANSA2
ANSC2
Bit 2
PS2
—
—
R/W-0/0
CPSOUT
CPSCH1
INLVLC1
INLVLA1
TRISA1
TRISC1
ANSA1
ANSC1
Bit 1
INTF
PS1
 2010 Microchip Technology Inc.
—
—
—
R/W-0/0
TMR1ON
CPSCH0
INLVLC0
INLVLA0
TRISA0
TRISC0
ANSC0
CPSCH<1:0>
ANSA0
T0XCS
IOCIF
Bit 0
PS0
—
—
R/W-0/0
Register
on Page
127
138
331
332
128
133
139
187
197
126
132
137
93
bit 0