PIC16F1828-E/SS Microchip Technology, PIC16F1828-E/SS Datasheet - Page 343

• Manufacturer Part Number: PIC16F1828-E/SS
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1828-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F1824/1828
BCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
BRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
BRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
BSF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41419B-page 342
Relative Branch
[ label ] BRA label
[ label ] BRA $+k
-256  label - PC + 1  255
-256  k  255
(PC) + 1 + k  PC
None
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
Bit Clear f
[ label ] BCF
0  f  127
0  b  7
0  (f<b>)
None
Bit ‘b’ in register ‘f’ is cleared.
Relative Branch with W
[ label ] BRW
None
(PC) + (W)  PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
Bit Set f
[ label ] BSF
0  f  127
0  b  7
1  (f<b>)
None
Bit ‘b’ in register ‘f’ is set.
f,b
f,b
Preliminary
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Clear
[ label ] BTFSC f,b
0  f  127
0  b  7
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0  f  127
0  b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
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