PIC18LF25K22-E/SP Microchip Technology, PIC18LF25K22-E/SP Datasheet - Page 290
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PIC18LF25K22-E/SP
Manufacturer Part Number
PIC18LF25K22-E/SP
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
16.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREGx register. If the RCxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE/GIEH bit is
also set, the program will branch to the interrupt vector.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS41412D-page 290
BAUDCON1
BAUDCON2
INTCON
IPR1
IPR3
PIE1
PIE3
PIR1
PIR3
PMD0
RCREG1
RCSTA1
RCREG2
RCSTA2
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TXSTA1
TXSTA2
Legend:
never Idle
Name
Reception”), with the following exceptions:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.
EUSART Synchronous Slave
Reception
UART2MD UART1MD TMR6MD TMR5MD TMR4MD
GIE/GIEH
ABDOVF
ABDOVF
SSP2IP
SSP2IE
SSP2IF
SPEN
SPEN
CSRC
CSRC
Bit 7
—
—
—
(Section 16.4.1.6 “Synchronous
PEIE/GIEL
BCL2IP
BCL2IE
BCL2IF
RCIDL
RCIDL
ADIP
ADIE
ADIF
Bit 6
RX9
RX9
TX9
TX9
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
TMR0IE
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
DTRXP
DTRXP
RC1IP
RC2IP
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
EUSART1 Receive Register
EUSART2 Receive Register
Preliminary
CKTXP
CKTXP
INT0IE
TX1IP
TX2IP
TX1IE
TX2IE
CREN
CREN
SYNC
SYNC
TX1IF
TX2IF
Bit 4
CTMUIP
CTMUIE
CTMUIF
SSP1IP
SSP1IE
ADDEN
ADDEN
SSP1IF
SENDB
SENDB
BRG16
BRG16
16.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
If using interrupts, ensure that the GIE/GIEH
and PEIE/GIEL bits of the INTCON register are
set and set the RCxIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCxIF bit will be set when reception is
complete. An interrupt will be generated if the
RCxIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTAx
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREGx register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTAx
register or by clearing the SPEN bit which resets
the EUSART.
TMR5GIP TMR3GIP TMR1GIP
TMR5GIE TMR3GIE TMR1GIE
TMR5GIF
TMR3MD
TMR0IF
CCP1IP
CCP1IE
CCP1IF
BRGH
BRGH
FERR
FERR
Bit 2
Synchronous Slave Reception
Setup:
—
—
TMR3GIF
TMR2MD
TMR2IP
TMR2IE
TMR2IF
INT0IF
OERR
OERR
TRMT
TRMT
2010 Microchip Technology Inc.
WUE
WUE
Bit 1
TMR1GIF
TMR1MD
TMR1IP
TMR1IE
TMR1IF
ABDEN
ABDEN
RX9D
RX9D
TX9D
TX9D
Bit 0
RBIF
Register
on Page
274
274
115
127
129
123
125
118
120
273
273
272
272
56
—
—
—
—
—
—
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