PIC24FJ16MC102-I/SO Microchip Technology, PIC24FJ16MC102-I/SO Datasheet - Page 28
![16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SOIC .300in TUBE](/photos/16/13/161315/soic28_sml.jpg)
PIC24FJ16MC102-I/SO
Manufacturer Part Number
PIC24FJ16MC102-I/SO
Description
16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheet
1.PIC24FJ16MC101-IP.pdf
(304 pages)
Specifications of PIC24FJ16MC102-I/SO
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-28
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Featured Product
PIC24FJ/33FJ MCUs & dsPIC® DSCs
Core Processor
PIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
21
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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PIC24FJ16MC101/102
4.1.1
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-2:
DS39997B-page 28
0x000001
0x000003
0x000005
0x000007
Address
msw
PROGRAM MEMORY
ORGANIZATION
Program Memory
PROGRAM MEMORY ORGANIZATION
‘Phantom’ Byte
(read as ‘0’)
most significant word (msw)
00000000
00000000
00000000
00000000
(Figure
23
4-2).
Preliminary
16
Instruction Width
least significant word (lsw)
4.1.2
All
addresses between 0x00000 and 0x000200 for hard-
coded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.
PIC24FJ16MC101/102 devices also have two interrupt
vector tables, located from 0x000004 to 0x0000FF and
0x000100 to 0x0001FF. These vector tables allow each
of the device interrupt sources to be handled by sepa-
rate Interrupt Service Routines (ISRs). A more detailed
discussion of the interrupt vector tables is provided in
Section 7.1 “Interrupt Vector
PIC24FJ16MC101/102
8
INTERRUPT AND TRAP VECTORS
© 2011 Microchip Technology Inc.
0
devices
Table”.
(lsw Address)
PC Address
0x000000
0x000002
0x000004
0x000006
reserve
the
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