PIC24FJ16MC102-I/SO Microchip Technology, PIC24FJ16MC102-I/SO Datasheet - Page 75
![16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SOIC .300in TUBE](/photos/16/13/161315/soic28_sml.jpg)
PIC24FJ16MC102-I/SO
Manufacturer Part Number
PIC24FJ16MC102-I/SO
Description
16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheet
1.PIC24FJ16MC101-IP.pdf
(304 pages)
Specifications of PIC24FJ16MC102-I/SO
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-28
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Featured Product
PIC24FJ/33FJ MCUs & dsPIC® DSCs
Core Processor
PIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
21
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 75 of 304
- Download datasheet (5Mb)
REGISTER 7-10:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
R/W-0
T2IE
U-0
—
Unimplemented: Read as ‘0’
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1EIE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE
R/W-0
U-0
—
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
‘1’ = Bit is set
W = Writable bit
R/W-0
AD1IE
R/W-0
IC2IE
U1TXIE
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U1RXIE
R/W-0
R/W-0
T1IE
PIC24FJ16MC101/102
SPI1IE
OC1IE
R/W-0
R/W-0
x = Bit is unknown
SPI1EIE
R/W-0
R/W-0
IC1IE
DS39997B-page 75
INT0IE
R/W-0
R/W-0
T3IE
bit 8
bit 0
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