PIC24FJ64GA110-E/PT Microchip Technology, PIC24FJ64GA110-E/PT Datasheet - Page 163

• Manufacturer Part Number: PIC24FJ64GA110-E/PT
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 100 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA110-E/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.0
Devices in the PIC24FJ256GA110 family all feature
9 independent enhanced input capture modules. Each
of the modules offers a wide range of configuration and
operating options for capturing external pulse events
and generating interrupts.
Key features of the enhanced output module include:
• Hardware-configurable for 32-bit operation in all
• Synchronous and Trigger modes of output
• A 4-level FIFO buffer for capturing and holding
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
The module is controlled through two registers: ICxCON1
(Register
block diagram of the module is shown in
FIGURE 13-1:
 2010 Microchip Technology Inc.
Note:
modes by cascading two adjacent modules
compare operation, with up to 30 user-selectable
trigger/sync sources available
timer values for several events
driving a separate internal 16-bit counter
Trigger and
Sync Sources
IC Clock
Sources
Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see
ICx Pin
INPUT CAPTURE WITH
DEDICATED TIMER
13-1) and ICxCON2
Section
Dedicated Timer” (DS39722)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
(1)
Pin Select”
ICTSEL<2:0>
Trigger and
Sync Logic
Prescaler
34.
Family
INPUT CAPTURE BLOCK DIAGRAM
Counter
1:1/4/16
Select
Clock
for more information.
“Input
(Register
Reference
Increment
Reset
Capture
13-2). A general
ICM<2:0>
Figure
SYNCSEL<4:0>
TRIGGER
Clock Synchronizer
Edge Detect Logic
Manual”,
13-1.
PIC24FJ256GA110 FAMILY
ICxTMR
and
with
13.1
13.1.1
By default, the enhanced input capture module oper-
ates in a free-running mode. The internal 16-bit counter
ICxTMR counts up continuously, wrapping around from
FFFFh to 0000h on each overflow, with its period
synchronized to the selected external clock source.
When a capture event occurs, the current 16-bit value
of the internal counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Standard, free-running operation is selected by setting
the SYNCSEL bits to ‘00000’ and clearing the ICTRIG
bit (ICxCON2<7>). Synchronous and Trigger modes
are selected any time the SYNCSEL bits are set to any
value except ‘00000’. The ICTRIG bit selects either
Synchronous or Trigger mode; setting the bit selects
Trigger mode operation. In both modes, the SYNCSEL
bits determine the sync/trigger source.
When the SYNCSEL bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
16
General Operating Modes
SYNCHRONOUS AND TRIGGER
MODES
4-Level FIFO Buffer
ICOV, ICBNE
ICI<1:0>
Event and
Interrupt
ICxBUF
Logic
(1)
Section 10.4 “Peripheral
Set ICxIF
DS39905E-page 163
16
System Bus
16