SST25VF064C-80-4C-Q2AE-T Microchip Technology, SST25VF064C-80-4C-Q2AE-T Datasheet - Page 10

• Manufacturer Part Number: SST25VF064C-80-4C-Q2AE-T
• Description: 2.7V To 3.6V 64Mbit SPI Serial Flash 8 TDFN 6x8x0.8mm T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF064C-80-4C-Q2AE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Read (33 MHz)
The Read instruction, 03H, supports up to 33 MHz Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high tran-
sition on CE#. The internal address pointer will automati-
cally increment until the highest memory address is
reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space. For exam-
High-Speed Read (80 MHz)
The High-Speed Read instruction supporting up to 80 MHz
Read is initiated by executing an 8-bit command, 0BH, fol-
lowed by address bits A
remain active low for the duration of the High-Speed Read
cycle. See Figure 7 for the High-Speed Read sequence.
Following a dummy cycle, the High-Speed Read instruction
outputs the data starting from the specified address loca-
tion. The data output stream is continuous through all
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. For example, once the data
from address location 7FFFFFH is read, the next output is
from address location 000000H.
©2010 Silicon Storage Technology, Inc.
FIGURE 6: Read Sequence
5. 32KByte Block Erase addresses: use A
6. 64KByte Block Erase addresses: use A
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A
9. Requires a prior WREN command.
device ID output stream is continuous until terminated by a low-to-high transition on CE#.
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0 1 2 3 4 5 6 7 8
23
-A
0
and a dummy byte. CE# must
03
HIGH IMPEDANCE
0
= 0, and Device ID is read with A
MS
MS
-A
-A
MSB
ADD.
15,
16,
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
15 16
ADD.
23 24
10
ADD.
0
= 1. All other address bits are 00H. The Manufacturer’s ID and
ple, once the data from address location 7FFFFFH has
been read, the next output will be from address location
000000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits A
remain active low for the duration of the Read cycle. See
Figure 6 for the Read sequence.
MSB
31 32
D
OUT
N
39 40
64 Mbit SPI Serial Dual I/O Flash
D
N+1
OUT
47 48
D
N+2
OUT
55 56
D
N+3
OUT
63 64
IL
IL
SST25VF064C
or V
or V
D
N+4
1392 F06.0
OUT
S71392-04-000
IH.
IH.
23
-A
70
0
. CE# must
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