SST25VF064C-80-4C-Q2AE-T Microchip Technology, SST25VF064C-80-4C-Q2AE-T Datasheet - Page 11

• Manufacturer Part Number: SST25VF064C-80-4C-Q2AE-T
• Description: 2.7V To 3.6V 64Mbit SPI Serial Flash 8 TDFN 6x8x0.8mm T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF064C-80-4C-Q2AE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Fast-Read Dual-Output (75 MHz)
The Fast-Read Dual-Output (3BH) instruction outputs data
up to 75 MHz from the SIO
instruction, execute an 8-bit command (3BH) followed by
address bits A23-A0 and a dummy byte on SI/SIO
lowing a dummy cycle, the Fast-Read Dual-Output instruc-
tion outputs the data starting from the specified address
location on the SIO
clock sequence, odd data bits D7, D5, D3, and D1; and
SIO
remain active low for the duration of the Fast-Read Dual-
Output instruction cycle. See Figure 8 for the Fast-Read
Dual-Output sequence.
©2010 Silicon Storage Technology, Inc.
FIGURE 7: High-Speed Read Sequence
FIGURE 8: Fast-Read Dual Output Sequence
SIO 0
SIO 1
SCK
CE#
0
outputs even data bits D6, D4, D2, and D0. CE# must
SCK
CE#
SO
MODE 3
MODE 0
SI
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8
1
and SIO
0 1 2 3 4 5 6 7 8
3B
0
HIGH IMPEDANCE
and SIO
0B
0
HIGH IMPEDANCE
lines. SIO
ADD.
1
pins. To initiate the
24-Bit Address
15 16
ADD.
1
ADD.
outputs, per
15 16
28 29 30 31
ADD.
ADD.
0
. Fol-
23 24
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
ADD.
11
31 32
Dummy Cycle
The data output stream is continuous through all
addresses until terminated by a low-to-high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer automatically increments to the beginning (wrap-
around) of the address space. for 64 Mbit density, once the
data from address location 7FFFFFH has been read the
next output will be from address location 000000H.
X
X
39 40
D OUT
MSB
N
47 48
7 5 3 1 7 5 3 1
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
MSB
DOUT
D OUT
IO, Switches from Input to Output
N+1
N
55 56
MSB
D OUT
N+2
DOUT
N+1
63 64
D OUT
N+3
7 5 3 1
MSB
DOUT
71 72
N+2
D OUT
N+4
1392 F07.0
S71392-04-000
80
7 5 3 1
MSB
DOUT
N+3
Data Sheet
1392 F08.1
04/10