SST25VF064C-80-4C-Q2AE-T Microchip Technology, SST25VF064C-80-4C-Q2AE-T Datasheet - Page 17

• Manufacturer Part Number: SST25VF064C-80-4C-Q2AE-T
• Description: 2.7V To 3.6V 64Mbit SPI Serial Flash 8 TDFN 6x8x0.8mm T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF064C-80-4C-Q2AE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. Initiate the Chip-Erase instruction by
Read Security ID
To execute a Read SID operation, the host drives CE# low,
sends the Read SID command cycle (88H), one address
cycle, and then one dummy cycle. Each cycle is eight bits
long, most significant bit first.
After the dummy cycle, the device outputs data on the fall-
ing edge of the SCK signal, starting from the specified
address location. The data output stream is continuous
through all SID addresses until terminated by a low-to-high
transition on CE#. The internal address pointer automati-
cally increments until the last SID address is reached, then
outputs wrap around until CE# goes high.
Lockout Security ID
The Lockout SID instruction prevents any future changes to
the Security ID. Prior to the Lockout SID operation, the
Write-Enable (WREN) instruction must be executed. To
execute a Lockout SID, the host drives CE# low, sends the
Lockout SID command cycle (85H), then drives CE# high.
A cycle is 8 bits long, most significant bit first. The user may
poll the BUSY bit in the software status register or waits
T
©2010 Silicon Storage Technology, Inc.
PSID
FIGURE 15: Chip-Erase Sequence
for the completion of the Lockout SID operation.
SCK
CE#
SO
SI
MODE 3
MODE 0
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
17
60 or C7
executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. Poll the Busy
bit in the software status register or wait T
tion of the internal self-timed Chip-Erase cycle. See Figure
15 for the Chip-Erase sequence.
Program Security ID
The Program SID instruction programs one to 24 bytes of
data in the user-programmable, Security ID space. The
device ignores a Program SID instruction pointing to an
invalid or protected address, see Table 7. Prior to the pro-
gram operation, execute WREN.
To execute a Program SID operation, the host drives CE#
low, sends the Program SID command cycle (A5H), one
address cycle, the data to be programmed, then drives
CE# high. The programmed data must be between 1 to 24
Bytes and in whole Byte increments. To determine the
completion of the internal, self-timed Program SID opera-
tion, poll the BUSY bit in the software status register, or wait
T
SID operation.
TABLE 7: Program Security ID
Program Security ID
Pre-Programmed at factory
User Programmable
PSID
for the completion of the internal self-timed Program
1392 F16.0
Address Range
00H – 07H
08H – 1FH
S71392-04-000
CE
for the comple-
Data Sheet
T7.0 1392
04/10