SY89221UHY Micrel Inc, SY89221UHY Datasheet

2.5V/3.3V Integrated Divider + Fanout With 15 LVPECL Outputs Asn FSI Inputs (I Temp, )

SY89221UHY

Manufacturer Part Number

SY89221UHY

Description

2.5V/3.3V Integrated Divider + Fanout With 15 LVPECL Outputs Asn FSI Inputs (I Temp, )

Manufacturer

Micrel Inc

Series

Precision Edge®r

Type

Fanout Buffer (Distribution), Divider, Multiplexerr

Datasheet

1.SY89221UHY.pdf (17 pages)

Specifications of SY89221UHY

Number Of Circuits

Ratio - Input:output

2:15

Differential - Input:output

Yes/Yes

Input

CML, LVDS, PECL

Output

LVPECL

Frequency - Max

2GHz

Voltage - Supply

2.375 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP

Frequency-max

2GHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

576-1616

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

SY89221UHY

Manufacturer:

Micrel Inc

Quantity:

10 000

Current page: 1 of 17
Download datasheet (829Kb)

General Description

The SY89221U is a 2.5/3.3V precision, high-speed,

integrated clock divider and LVPECL fanout buffer

capable of handling clocks up to 1.5GHz. Optimized

for

independently controlled output banks are phase-

matched and can be configured for pass through ÷1,

÷2 or ÷4 divider ratios.

The differential input includes Micrel’s unique, 3-pin

input termination architecture that allows the user to

interface to any differential signal (AC- or DC-coupled)

as small as 100mV (200mV

shifting or termination resistor networks in the signal

path. The low-skew, low-jitter outputs are LVPECL

compatible with extremely fast rise/fall times that are

guaranteed to be less than 220ps.

The /MR (master reset) input asynchronously resets

the outputs. A four-clock delay after de-asserting /MR

allows the counters to synchronize and start the

outputs from the same state without any runt pulse.

The SY89221U is part of Micrel’s Precision Edge

product family. All support documentation can be

found at Micrel's web site at: www.micrel.com.

Precision Edge is a registered trademark of Micrel, Inc.

August 2007

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

communications

applications,

) without any level

the

four

Precision 1:15 LVPECL Fanout Buffer with

2:1 MUX and Four ÷1/÷2/÷4 Clock Divider

408

Features

• Four low-skew LVPECL output banks with

• Four output banks, 15 total outputs

• Guaranteed AC performance over temperature and

• Fail Safe Input

• Ultra-low jitter design:

• Patent-pending input termination and VT pin

• CMOS/TTL-compatible output enable (EN) and

• 2.5V ±5% or 3.3V ±10% power supply

• –40°C to +85°C temperature range

• Available in 64-pin TQFP

Applications

• All SONET/SDH applications

• All Fibre Channel applications

• All Gigabit Ethernet applications

Markets

• LAN/WAN routers/switches

• Enterprise servers

• Storage

• ATE

• Test and measurement

) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

independently programmable ÷1, ÷2 and ÷4 divider

options

voltage:

– Accepts a clock frequency up to 1.5GHz

– <1600ps IN-to-OUT propagation delay

– <270ps rise/fall time

– <35 ps within-bank skew

– Prevents outputs from oscillating

– <1ps

– <10ps

accepts DC- and AC-coupled inputs (CML, PECL,

LVDS)

divider select control

RMS

random jitter

total jitter (clock)

Output Banks

SY89221U

hbwhelp@micrel.com

or (408) 955-1690

M9999-082407-C

Related parts for SY89221UHY

SY89221UHY Summary of contents

Page 1

... All support documentation can be found at Micrel's web site at: www.micrel.com. Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( August 2007 Precision 1:15 LVPECL Fanout Buffer with 2:1 MUX and Four ÷1/÷2/÷4 Clock Divider Features • ...

Page 2

Functional Block Diagram August 2007 2 hbwhelp@micrel.com M9999-082407-C or (408) 955-1690 ...

Page 3

... Contact factory for die availability. Dice are guaranteed Tape and Reel. Pin Configuration August 2007 Operating Package Marking Type Range Industrial SY89221UHY with Pb-Free bar-line indicator SY89221UHY with T64-1 Industrial Pb-Free bar-line indicator = 25°C, DC Electricals only. A 64-Pin EPAD-TQFP (T64-1) 3 Lead Finish Pb-Free ...

Page 4

Pin Description Pin Number Pin Name 1, 2 FSELA1, FSELA0 3, 4 FSELB1, FSELB0 15, 16 FSELC1, FSELC0 17, 18 FSELD1, FSELD0 5, 8, IN0, /IN0 11, 14 IN1, /IN1 6, 12 VT0, VT1 7, VREF-AC0, 13 VREF-AC1 9 /MR ...

Page 5

Pin Description (continued) Pin Number Pin Name 64 EN 19, 32, 49, 63 GND, Exposed Pad Function Table (1) (2, 3) /MR EN CLK_SEL ...

Page 6

Absolute Maximum Ratings Supply Voltage (V ) ............................... –0.5V to +4.0V CC Input Voltage (V ) .......................................–0. Termination Current Source or sink current LVPECL Output Current (I ) OUT Continuous.......................................................50mA Surge .............................................................100mA Input Current ...

Page 7

LVTTL/CMOS DC Electrical Characteristics V = +2.5V ±5% or 3.3V ±10 Symbol Parameter V Input HIGH Voltage IH V Input LOW Voltage IL I Input HIGH Current IH I Input LOW Current IL LVPECL Outputs DC Electrical Characteristics ...

Page 8

AC Electrical Characteristics V = +2.5V ±5% or 3.3V ±10 Symbol Parameter f Maximum Operating Frequency MAX t Differential Propagation Delay PD t Reset Recovery Time RR t Differential Propagation Delay PD Tempco Temperature Coefficient t Within-Bank Skew ...

Page 9

Functional Description Clock Select (CLK_SEL) CLK_SEL is an asynchronous TTL/CMOS compatible input that selects one of the two input signals. Internal 25kΩ pull-up resistor defaults the input to logic HIGH if left open. Delay between the clock selection and multiplexer ...

Page 10

Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Timing Diagrams August 2007 Figure 1b. Differential Voltage Swing Figure 2a. Propagation Delay Figure 2b. Fail Safe Feature 10 M9999-082407-C hbwhelp@micrel.com or (408) 955-1690 ...

Page 11

Micrel, Inc. Timing Diagrams August 2007 Figure 2c. Reset with Output Enabled 11 SY89221U M9999-082407-C hbwhelp@micrel.com or (408) 955-1690 ...

Page 12

Timing Diagrams August 2007 Figure 2d. Enable Timing Figure 2e. Disable Timing 12 M9999-082407-C hbwhelp@micrel.com or (408) 955-1690 ...

Page 13

Typical Operating Characteristics V = 3.3V, GND = 0V 100mV August 2007 = 50Ω -2V 25°C, unless otherwise stated M9999-082407-C hbwhelp@micrel.com or (408) 955-1690 ...

Page 14

Functional Characteristics V = 3.3V, GND = 0V 100mV August 2007 = 50Ω -2V 25°C, unless otherwise stated M9999-082407-C hbwhelp@micrel.com or (408) 955-1690 ...

Page 15

Input and Output Stages Figure 3a. Simplified Differential Input Stage Input Interface Applications Figure 4a. CML Interface (DC-Coupled) May connect Figure 4d. LVPECL Interface (AC-Coupled) August 2007 Figure 3b. Simplified Differential Output Stage Figure 4b. ...

Page 16

LVPECL Output Interface Applications LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω- and 100Ω-controlled transmission lines. There are several techniques for ...

Page 17

Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. ...

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