SY89221UHY Micrel Inc, SY89221UHY Datasheet - Page 8

• Manufacturer Part Number: SY89221UHY
• Description: 2.5V/3.3V Integrated Divider + Fanout With 15 LVPECL Outputs Asn FSI Inputs (I Temp, )
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of SY89221UHY

• Number Of Circuits: 1
• Ratio - Input:output: 2:15
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, PECL
• Output: LVPECL
• Frequency - Max: 2GHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1616

AC Electrical Characteristics
V
Notes:
8.
9.
10. Skews within banks depend on the number of outputs. Within-bank skew decreases if the bank has lesser outputs.
11. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
13. Random jitter is measured with a K28.7 comma detect character pattern.
14. Total jitter definition: with an ideal clock input frequency ≤ f
15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
Symbol
f
t
t
t
Tempco
t
t
t
August 2007
CC
MAX
PD
RR
PD
SKEW
JITTER
r,
t
f
Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed
by design and characterization.
Within-bank skew is the difference in propagation delays among the outputs within the same bank.
between each bank, after MR is applied.
respective inputs.
specified peak-to-peak jitter value.
signal.
= +2.5V ±5% or 3.3V ±10%, T
Parameter
Maximum Operating Frequency
Differential Propagation Delay
Reset Recovery Time
Differential Propagation Delay
Temperature Coefficient
Within-Bank Skew
Bank-to-Bank Skew
Bank-to-Bank Skew
Part-to-Part Skew
Random Jitter (RJ)
Total Jitter (TJ)
Cycle-to-Cycle Jitter
Output Rise/Fall Time
(20% to 80%)
Duty Cycle
A
= –40°C to +85°C, R
(8)
Condition
V
IN-to-Q
CLK_SEL-to-Q
/MR(H-L)-to-Q
/MR (L-H)-to-IN
Within same fanout bank
Same divide setting
Different divide setting
Note 12
Note 13
Note 14
Note 15
At full output swing
Divide-by-2 or Divide-by-4
Divide-by-1, input > 1GHz
Divide-by-1, input < 1GHz
OUT
≥ 400mV
MAX
, no more than one output edge in 10
L
= 50Ω to V
8
(11)
(11)
(9, 10)
CC
n
–T
–2V, unless otherwise stated.
n–1
where T is the time between rising edges of the output
[e-mail]
12
output edges will deviate by more than the
Min
800
700
700
300
120
1.5
47
45
47
1250
1000
1000
Typ
225
180
2.0
10
15
25
or [phone]
M9999-082407-C
1600
1400
1400
Max
400
270
35
40
60
10
53
55
53
1
1
Units
ps
ps
fs/°C
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
RMS
RMS
PP