SY89221UHY Micrel Inc, SY89221UHY Datasheet - Page 4

2.5V/3.3V Integrated Divider + Fanout With 15 LVPECL Outputs Asn FSI Inputs (I Temp, )

SY89221UHY

Manufacturer Part Number
SY89221UHY
Description
2.5V/3.3V Integrated Divider + Fanout With 15 LVPECL Outputs Asn FSI Inputs (I Temp, )
Manufacturer
Micrel Inc
Series
Precision Edge®r
Type
Fanout Buffer (Distribution), Divider, Multiplexerr
Datasheet

Specifications of SY89221UHY

Number Of Circuits
1
Ratio - Input:output
2:15
Differential - Input:output
Yes/Yes
Input
CML, LVDS, PECL
Output
LVPECL
Frequency - Max
2GHz
Voltage - Supply
2.375 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
Frequency-max
2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-1616

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SY89221UHY
Manufacturer:
Micrel Inc
Quantity:
10 000
Pin Description
August 2007
20, 25, 30, 33,
41, 48, 50, 55,
Pin Number
34, 35,
38, 39,
44, 45,
15, 16
17, 18
11, 14
21, 22
23, 24
26, 27
28, 29
36, 37
42, 43
46, 47
51, 52
53, 54
56, 57
58, 59
60, 61
6, 12
5, 8,
1, 2
3, 4
13
10
40
62
31
7,
9
FSELC1, FSELC0
FSELD1, FSELD0
FSELA1, FSELA0
FSELB1, FSELB0
VREF-AC0,
VREF-AC1
/QC0, QC0
/QC1, QC1
/QC2, QC2
/QC3, QC3
/QD0, QD0
/QD1, QD1
/QD2, QD2
/QD3, QD3
/QD4, QD4
/QD5, QD5
/QA0, QA0
/QA1, QA1
/QB0, QB0
/QB1, QB1
/QB2, QB2
Pin Name
CLK_SEL
VT0, VT1
IN0, /IN0
IN1, /IN1
VCC
/MR
NC
Pin Function
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the four
banks of outputs. Note that each of these inputs is internally connected to a 25kΩ pull-up
resistor and will default to a logic HIGH state if left open. The input-switching threshold is
V
Differential Inputs: These input pairs are the differential signal inputs to the device. They
accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50Ω. Note that these inputs will default to an indeterminate
state if left open. Please refer to the “Input Interface Applications” section for more
details.
Input Termination Center-Tap: Each side of a differential input pair terminates to a VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “ Input Interface Applications” section for more details.
Reference Voltage: These outputs bias to V
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01µF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA.
Please refer to the “Input Interface Applications” section for more details.
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state as
long as /MR remains LOW. This input is internally connected to a 25kΩ pull-up resistor
and will default to logic HIGH state if left open. The input-switching threshold is V
Single-Ended Input: This TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will
default to logic HIGH state if left open. The input-switching threshold is V
Positive Power Supply. Bypass with a 0.1µF||0.01µF low ESR capacitor as close to V
pin as possible.
Bank C LVPECL differential output pairs controlled by FSELC0 and FSELC1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50Ω terminated to V
No connect.
Bank D LVPECL differential output pairs controlled by FSELD0 and FSELD1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50Ω terminated to V
Bank A LVPECL differential output pairs controlled by FSELA0 and FSELA1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50Ω terminated to V
Bank B LVPECL differential output pairs controlled by FSELB0 and FSELB1. Refer to
“Function Table” for details. Unused output pairs may be left open. Each output is
designed to drive 800mV into 50Ω terminated to V
CC
/2.
4
CC
–1.2V. They are used for AC-coupling
hbwhelp@micrel.com
CC
CC
CC
CC
– 2V.
– 2V.
– 2V.
– 2V.
or (408) 955-1690
M9999-082407-C
CC
/2.
CC
/2.
CC

Related parts for SY89221UHY