XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 55

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D.3.1 Timer Mode:
Please note that of the two C/T Modes, the Timer Mode is
the only mode which is relevant to the function of Bit Rate
Selection.
Mode is also discussed here.
In the Timer mode, the C/T acts as a programmable
divider and generates a square wave whose period is
twice the value (in clock periods) of the contents of the
Counter/Timer Registers, CTUR and CTLR. The C/T can
be used as a programmable bit rate generator in order to
produce a 16X clock for any bit rate not provided by the
BRG. The square-wave, originating from the C/T is
output on Output Port pin, OP3.
If the C/T is programmed to operate in the Timer mode,
the frequency of the resulting C/T square wave can be
expressed as follows:
C/T Output Frequency =
Where: [CTUR] = the contents of the CTUR register in
Since the C/T Output is handled as a 16X clock signal by
the DUART circuitry, the resulting bit rate is 1/16 the
frequency of the C/T Output signal. Therefore, the bit
rate, derived from the C/T can be expressed as follows:
Bit Rate =
The contents of the CTUR and CTLR registers may be
changed at any time, but will only begin to take effect at
the next half cycle of the square wave. The C/T begins
operation using the values in CTUR/CTLR upon receipt of
the Address-Trigger “START COUNTER” command (See
Table 1).
The C/T then runs continuously. A subsequent “START
COUNTER” command causes the C/T to terminate the
current timing cycle and begin a new timing cycle using
the current values stored in CTUR and CTLR. The
COUNTER READY status bit, in the Interrupt Status
Register (ISR[3]), is set once each cycle of the square
wave. This allows the use of the C/T as a periodic
Rev. 2.11
decimal form
[CTUR] = the contents of the CTLR register in
decimal form
Frequency of Selected Timing Source
Frequency of Selected Timing Source
However, for completeness, the Counter
32·([CTUR]·2
2·([CTUR]·2
8
8
+ [CTLR] )
+ [CTLR] )
55
interrupt generator, if the condition is programmed to
generate an interrupt via the interrupt mask register
(IMR).
address-triggered “STOP COUNTER” command (See
Table 1). In the TIMER mode, however, the command
does not actually stop the C/T.
D.3.2 COUNTER MODE
In the Counter Mode, the C/T counts down the number of
pulses written into CTUR/CTLR, beginning at the receipt
of
COUNTER/READY status bit (ISR[3]) is set upon
reaching the count of 0000
count past the 0000
being FFFF
COUNTER” command. If OP3 is programmed to be the
output of the C/T, the output will remain high until the
terminal count is reached, at which time the output goes
low. It then returns to the high state and ISR[3] is cleared
when the C/T is stopped (via the “STOP COUNTER”
command). A “START COUNTER” command while the
counter is running restarts the counter with the values in
CTUR/CTLR. The CPU may change the contents of
CTUR or CTLR at any time but the new count takes effect
only on after the subsequent START COUNTER
command.
previous values are preserved and used for the next
cycle.
D.4 External Inputs
The DUART allows for some of the Input Port pins (IP2 -
IP5) to be used as direct external inputs to the Timing
Control Block as timing sources for the Transmitters and
Receivers of both channels. Please note that the user can
specify whether a clock signal, applied to one of these
external inputs, is a 1X or a 16X clock signal; via the Clock
Select Registers (see Section D.5). For a more detailed
discussion on the Input Port pins and their function,
please see Section E.
D.5 Clock Select Registers, CSRA and CSRB
In Figure 24, the Clock Select Registers are the 32:1
MUX’s. The Clock Select Registers are the means that
the user can select which clock signals will drive the
Transmitters and Receivers of both channels. The CSRs
allow the user to select the 23 different standard bit rates
from the BRG, the Counter/Timer output, or to use an
external input as the timing source for the Transmitters
a
The ISR[3] can be cleared by issuing the
“START
16
If new values are not programmed the
) until it is stopped by the CPU via a “STOP
16
COUNTER”
and underflow (with the next count
16
XR88C681
. The C/T will continue to
command.
The