AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 122

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

14-13 DATA_SCALE
12-9
8
7-2
1-0
122
PWR_STATE Power State. This 2-bit field is
DATA_SEL Data Select. This optional four-bit
PME_EN
RES
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
only field indicates the scaling
factor to be used when interpret-
ing the value of the Data register.
The value and meaning of this
field will vary depending on the
DATA_SCALE field.
field is used to select which data
is reported through the Data reg-
ister and DATA_SCALE field.
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
PME_EN enables the function to
assert PME. When a 0, PME as-
sertion is disabled.
tion does not support PME gener-
ation from D3cold.
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
Sticky bit. This bit is reset by
POR. H_RESET, S_RESET, or
setting the STOP bit has no ef-
fect.
used both to determine the cur-
rent power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
Read/write accessible always.
Data Scale. This two bit read-
Read only.
Read/write accessible always.
PME
This bit defaults to “0” if the func-
If the function supports PME from
Read/write accessible always.
Reserved locations. Read only.
Enable.
When
P R E L I M I N A R Y
Am79C973/Am79C975
a
1,
PCI PMCSR Bridge Support Extensions Register
Offset 46h
Bit
7-0
PCI Data Register
Offset 47h
Note: All bits of this register are loaded from EE-
PROM. The register is aliased to lower bytes of the
BCR37-44 for testing purposes.
Bit
7-0
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C973/Am79C975 controller. The RAP contains
the address of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
PMCSR_BSE The PCI PMCSR Bridge Support
Name
Name
DATA_REG The PCI Data Register is an 8-bit
00b - D0.
01b - D1.
10b - D2.
11b - D3.
These bits can be written and
read, but their contents have no
effect on the operation of the de-
vice.
Read/write accessible always.
Description
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
The PCI PMCSR Bridge Support
Extensions register is located at
offset 46h in the PCI Configura-
tion Space. It is read only.
Description
register. Refer to the “PCI Bus
Power Management Interface
Specification” version 1.1 for a
more detailed description of this
register.
The PCI DATA register is located
at offset 47h in the PCI Configu-
ration Space. It is read only.