AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 52

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

RTABORT (PCI Status register, bit 12) will be set to
indicate that the Am79C973/Am79C975 controller has
received a target abort. In addition, SINT (CSR5, bit 11)
will be set to 1. When SINT is set, INTA is asserted if
the enable bit SINTE (CSR5, bit 10) is set to 1. This
mechanism can be used to inform the driver of the sys-
tem error. The host can read the PCI Status register to
determine the exact cause of the interrupt.
Master Initiated Termination
There are three scenarios besides normal completion
of a transaction where the Am79C973/Am79C975 con-
troller will terminate the cycles it produces on the PCI
bus.
Preemption During Non-Burst Transaction
When the Am79C973/Am79C975 controller performs
multiple non-burst transactions, it keeps REQ asserted
until the assertion of FRAME for the last transaction.
When GNT is removed, the Am79C973/Am79C975
controller will finish the current transaction and then re-
lease the bus. If it is not the last transaction, REQ will
52
DEVSEL
FRAME
STOP
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
ADDR i
Figure 17. Disconnect Without Data Transfer
0111
3
PAR
P R E L I M I N A R Y
4
DATA
0000
Am79C973/Am79C975
5
PAR
6
remain asserted to regain bus ownership as soon as
possible. See Figure 19.
Preemption During Burst Transaction
When the Am79C973/Am79C975 controller operates
in burst mode, it only performs a single transaction per
bus mastership period, where transaction is defined as
one address phase and one or multiple data phases.
The central arbiter can remove GNT at any time during
the transaction. The Am79C973/Am79C975 controller
will ignore the deassertion of GNT and continue with
data transfers, as long as the PCI Latency Timer is not
expired. When the Latency Timer is 0 and GNT is deas-
serted, the Am79C973/Am79C975 controller will finish
the current data phase, deassert FRAME, finish the
last data phase, and release the bus. If EXTREQ
(BCR18, bit 8) is cleared to 0, it will immediately assert
REQ to regain bus ownership as soon as possible. If
EXTREQ is set to 1, REQ will stay asserted.
7
8
9
10
ADDR i
0111
11
21510D-22