AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 96

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

SRAM Configuration
The Am79C973/Am79C975 controller supports inter-
nal SRAM as a FIFO extension as well as providing a
read/write data path to the SRAM. The Am79C973/
Am79C975 controller contains 12 Kbytes of SRAM.
Internal SRAM Configuration
The SRAM_SIZE (BCR25, bits 7-0) programs the size
of the SRAM. SRAM_SIZE can be programmed to a
smaller value than 12 Kbytes.
The SRAM should be programmed on a 512-byte
boundary. However, there should be no accesses to the
RAM space while the Am79C973/Am79C975 control-
ler is running. The Am79C973/Am79C975 controller
assumes that it completely owns the SRAM while it is
in operation. To specify how much of the SRAM is allo-
cated to transmit and how much is allocated to receive,
the user should program SRAM_BND (BCR26, bits 7-
0) with the page boundary where the receive buffer be-
gins. The SRAM_BND also should be programmed on
a 512-byte boundary. The transmit buffer space starts
at 0000h. It is up to the user or the software driver to
split up the memory for transmit or receive; there is no
defaulted value. The minimum SRAM size required is
four 512-byte pages for each transmit and receive
queue, which limits the SRAM size to be at least 4
Kbytes.
The SRAM_BND upon H_RESET will be reset to
0000h. The Am79C973/Am79C975 controller will not
have any transmit buffer space unless SRAM_BND is
programmed. The last configuration parameter neces-
sary is the clock source used to control the Expansion
Bus interface. This is programmed through the SRAM
Interface Control register. The externally driven Expan-
sion Bus Clock (EBCLK) can be used by specifying a
value of 010h in EBCS (BCR27, bits 5-3). This allows
the user to utilize any clock that may be available.
There are two standard clocks that can be chosen as
well, the PCI clock or the externally provided time base
clock. When the PCI or time base clock is used, the
EBCLK does not have to be driven, but it must be tied
to VDD through a resistor. The user must specify an
SRAM clock (BCR27, bits 5-3) that will not stop unless
the Am79C973/Am79C975 controller is stopped. Oth-
erwise, the Am79C973/Am79C975 controller will re-
port buffer overflows, underflows, corrupt data, and will
hang eventually.
The user can decide to use a fast clock and then divide
down the frequency to get a better duty-cycle if re-
quired. The choices are a divide by 2 or 4 and is pro-
grammed by the CLK_FAC bits (BCR27, bits 2-0). Note
that the Am79C973/Am79C975 controller does not
support an SRAM frequency above 33 MHz regardless
of the clock and clock factor used.
96
P R E L I M I N A R Y
Am79C973/Am79C975
No SRAM Configuration
If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the
SRAM size register, the Am79C973/Am79C975 con-
troller will assume that there is no SRAM present and
will reconfigure the four internal FIFOs into two FIFOs,
one for transmit and one for receive. The FIFOs will op-
erate the same as in the PCnet-PCI II controller. When
the SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM
BND (BCR26, bits 7-0) are ignored by the Am79C973/
Am79C975 controller. See Figure 46.
Low Latency Receive Configuration
If the LOLATRX (BCR27, bit 4) bit is set to 1, then the
Am79C973/Am79C975 controller will configure itself
for a low latency receive configuration. In this mode,
SRAM is required at all times. If the SRAM_SIZE
(BCR25, bits 7- 0) value is 0, the Am79C973/
Am79C975 controller will not configure for low latency
receive mode. The Am79C973/Am79C975 controller
will provide a fast path on the receive side bypassing
the SRAM. All transmit traffic will go to the SRAM, so
SRAM_BND (BCR26, bits 7-0) has no meaning in low
l ate nc y r e c ei ve m od e. Wh en th e Am 79 C9 73 /
Am79C975 controller has received 16 bytes from the
network, it will start a DMA request to the PCI Bus In-
terface Unit. The Am79C973/Am79C975 controller will
not wait for the first 64 bytes to pass to check for colli-
sions in Low Latency Receive mode. The Am79C973/
Am79C975 controller must be in STOP before switch-
ing to this mode. See Figure 47.
CAUTION: To provide data integrity when switching
into and out of the low latency mode, DO NOT SET
the FASTSPNDE bit when setting the SPND bit. Re-
ce iv e f ra me s WI LL b e ove rw ri t t en a n d t h e
Am79C973/Am79C975 controller may give erratic
behavior when it is enabled again.
Direct SRAM Access
The SRAM can be accessed through the Expansion
Bus Data port (BCR30). To access this data port, the
user must load the upper address EPADDRU (BCR29,
bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the
user will load the lower 16 bits of address EPADDRL
(BCR28, bits 15-0). To initiate a read, the user reads
the Expansion Bus Data Port (BCR30). This slave ac-
cess from the PCI will result in a retry for the very first
access. Subsequent accesses may give a retry or not,
depending on whether or not the data is present and
valid. The direct SRAM access uses the same FLASH/
EPROM access except for accessing the SRAM in
word format instead of byte format. This access is
meant to be a diagnostic access only. The SRAM can
only be accessed while the Am79C973/Am79C975
controller is in STOP or SPND (FASTSPNDE is set to
0) mode.