SC68C752BIB48-S NXP Semiconductors, SC68C752BIB48-S Datasheet - Page 21
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SC68C752BIB48-S
Manufacturer Part Number
SC68C752BIB48-S
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SC68C752BIB48-S.pdf
(48 pages)
Specifications of SC68C752BIB48-S
Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Number Of Channels
2
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SC68C752B_4
Product data sheet
7.1 Receiver Holding Register (RHR)
7.2 Transmit Holding Register (THR)
Remark: Refer to the notes under
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the line control register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
Table 10
for more register access information.
SC68C752B
© NXP B.V. 2010. All rights reserved.
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