SC68C752BIB48-S NXP Semiconductors, SC68C752BIB48-S Datasheet - Page 26
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SC68C752BIB48-S
Manufacturer Part Number
SC68C752BIB48-S
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SC68C752BIB48-S.pdf
(48 pages)
Specifications of SC68C752BIB48-S
Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Number Of Channels
2
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SC68C752B_4
Product data sheet
7.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
mode, data set, or peripheral device to the processor. It also indicates when a control
input from the modem changes state.
per channel.
Table 16.
[1]
Bit
7
6
5
4
3
2
1
0
The primary inputs RIn, CDn, CTSn, DSRn are all active LOW, but their registered equivalents in the MSR
and MCR (in Loopback mode) registers are active HIGH.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
[1]
[1]
[1]
[1]
Description
CD (active HIGH, logic 1). This bit is the complement of the CDn input during
normal mode. During internal Loopback mode, it is equivalent to the state of
MCR[3].
RI (active HIGH, logic 1). This bit is the complement of the RIn input during
normal mode. During internal Loopback mode, it is equivalent to the state of
MCR[2].
DSR (active HIGH, logic 1). This bit is the complement of the DSRn input
during normal mode. During internal Loopback mode, it is equivalent to the
state of MCR[0].
CTS (active HIGH, logic 1). This bit is the complement of the CTSn input
during normal mode. During internal Loopback mode, it is equivalent to the
state of MCR[1].
ΔCD. Indicates that CDn input (or MCR[3] in Loopback mode) has changed
state. Cleared on a read.
ΔRI. Indicates that RIn input (or MCR[2] in Loopback mode) has changed
state from LOW to HIGH. Cleared on a read.
ΔDSR. Indicates that DSRn input (or MCR[0] in Loopback mode) has changed
state. Cleared on a read.
ΔCTS. Indicates that CTSn input (or MCR[1] in Loopback mode) has changed
state. Cleared on a read.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
Table 16
shows Modem Status Register bit settings
SC68C752B
© NXP B.V. 2010. All rights reserved.
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