ISP1507D1HNUM STEricsson, ISP1507D1HNUM Datasheet - Page 48

• Manufacturer Part Number: ISP1507D1HNUM
• Manufacturer: STEricsson

Specifications of ISP1507D1HNUM

• Lead Free Status / RoHS Status: Compliant

Table 28.
Table 29.
CD00269906
Product data sheet
Bit
Symbol
Reset
Access
Bit
7
6
5
4
3
2
1
0
Symbol
USE_EXT_
VBUS_IND
DRV_VBUS_EXT
DRV_VBUS
CHRG_VBUS
DISCHRG_VBUS
DM_PULLDOWN
DP_PULLDOWN
-
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description
USE_EXT_
VBUS_IND
11.1.5 USB_INTR_EN_R_E register
R/W/S/C
7
0
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all
transitions are enabled.
VBUS_EXT
Description
Use external V
indicator.
0b — Use the internal OTG comparator.
1b — Use the external V
Drive V
0b — Do not drive PSW_N to LOW, disabling V
1b — Drive PSW_N to LOW, enabling V
Drive V
then setting DRV_VBUS is optional.
Charge V
first check that V
DM data lines have been LOW (SE0) for 2 ms.
0b — Do not charge V
1b — Charge V
Discharge V
for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0
to stop the discharge.
0b — Do not discharge V
1b — Discharge V
DM pull down: Enables the 15 kΩ pull-down resistor on DM.
0b — Pull-down resistor is not connected to DM.
1b — Pull-down resistor is connected to DM.
DP pull down: Enables the 15 kΩ pull-down resistor on DP.
0b — Pull-down resistor is not connected to DP.
1b — Pull-down resistor is connected to DP.
reserved; writing logic 1 will give undefined results
R/W/S/C
DRV_
6
0
BUS
BUS
BUS
: Signals the
external: Controls the external V
BUS
: Charges V
R/W/S/C
BUS
BUS
DRV_
VBUS
: Discharges V
BUS
BUS
5
0
.
indicator: Informs the
is discharged (see the DISCHRG_VBUS bit), and that both the DP and
.
BUS
Rev. 03 — 28 July 2010
Table 30
ISP1507D1
BUS
BUS
BUS
.
R/W/S/C
valid indicator signal input from the FAULT pin.
.
CHRG_
through a resistor. Used for the V
VBUS
BUS
4
0
shows the bit allocation of the register.
through a resistor. If the link sets this bit to logic 1, it waits
to drive 5 V on V
BUS
DISCHRG_
ULPI HS USB host and peripheral transceiver
R/W/S/C
ISP1507D1
.
VBUS
BUS
3
0
BUS
supply through the RESET_N/PSW_N pin.
.
BUS
DM_PULL
to use an external V
R/W/S/C
DOWN
. If DRV_VBUS_EXT is set to logic 1,
2
1
BUS
pulsing SRP. The link must
DP_PULL
ISP1507D1
R/W/S/C
DOWN
© ST-ERICSSON 2010. All rights reserved.
1
1
BUS
overcurrent
reserved
R/W/S/C
0
0
48 of 73