ISP1507D1HNUM STEricsson, ISP1507D1HNUM Datasheet - Page 8

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ISP1507D1HNUM

Manufacturer Part Number
ISP1507D1HNUM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1507D1HNUM

Lead Free Status / RoHS Status
Compliant
CD00269906
Product data sheet
8.6.1
8.4 Voltage regulator
8.5 Crystal oscillator and PLL
8.6 V
For details on controlling resistor settings, see
The ISP1507D1 contains a built-in voltage regulator that conditions the V
inside the ISP1507D1. The voltage regulator:
Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For
details, see
The ISP1507D1 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation.
The crystal oscillator takes a sine-wave input from an external crystal on the XTAL1 pin,
and converts it to a square wave clock for internal use. Alternatively, a square wave clock
of the same frequency can also be directly driven into the XTAL1 pin. Using an existing
square wave clock can save the cost of the crystal and also reduce the board size.
The PLL takes the square wave clock from the crystal oscillator, and multiplies or divides it
into various frequencies for internal use.
The PLL produces the following frequencies, irrespective of the clock source:
The ISP1507D1 provides three comparators, V
comparator, and session end comparator, to detect the V
This comparator is used by hosts and A-devices to determine whether the voltage on
V
valid comparator is 4.4 V. Any voltage on V
During power-up, it is expected that the comparator output will be ignored.
V
BUS
BUS
BUS
Squelch circuit to detect high-speed bus activity
High-speed disconnect detector
45 Ω high-speed bus terminations on DP and DM for peripheral and host modes
1.5 kΩ pull-up resistor on DP for full-speed peripheral mode
15 kΩ bus terminations on DP and DM for host and OTG modes
Supports input supply range of 3.0 V < V
Supplies internal circuitry with 1.8 V and 3.3 V
60 MHz clock for the ULPI controller
1.5 MHz for the low-speed USB data
12 MHz for the full-speed USB data
480 MHz for the high-speed USB data
Other internal frequencies for data conversion and data recovery
is at a valid level for operation. The ISP1507D1 minimum threshold for the V
comparators
valid comparator
Section
17.
Rev. 03 — 28 July 2010
ULPI HS USB host and peripheral transceiver
BUS
CC
Table
BUS
below this threshold is considered invalid.
< 3.6 V
valid comparator, session valid
8.
BUS
voltage level.
ISP1507D1
© ST-ERICSSON 2010. All rights reserved.
CC
supply for use
BUS
8 of 73

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